Abstract: The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first stage circuit having two or more first inputs which generates one or more first outputs; and a second stage circuit having at least one second input and at least one second output, wherein the one or more first outputs are the same as the at least one second input, wherein at least one of the group consisting of the first stage circuit and the second stage circuit includes either a pseudo AND gate or a pseudo NAND gate. This invention presents a method of decoding, comprising the steps of generating a signal responsive to two or more address bits and enabling a decoder by the generated signal.