Abstract: An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links coupling the first chip to the second chip. One of the links carries a clock signal between the chips. Other links carrying data have propagation delays different from the propagation delay of the link carrying the clock signal. The relation of the delays for the data links to the delay for the clock link determines a particular setup and/or hold time tested.
Abstract: The present invention provides a method and system for creating a test script. The invention begins processing when a user requests the automatic creation of a test script. When the user next enters data on a graphical user interface, the data is sent to a display server which manages the input and output on the graphical user interface. The display server creates an event corresponding to the type of input entered on the graphical user interface.In order to examine the context within which the event occurred, the present invention interposes a new version of a routine into the system so that the new routine is called when the GUI program attempts to retrieve the event from the display server buffer. Interposing ensures that the new version of the routine will be invoked before the original version of the routine.
Abstract: Apparatus, methods, and computer program products are disclosed to simplify a computer user's handling of electronic mail messages. The invention provides the computer user with a mechanism for ignoring a particular ongoing e-mail discussion until that ongoing discussion terminates.
Abstract: In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node.