Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.

Abstract: The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.