Abstract: A method of smoothing Kalman Filter position states forming a "groundtrack" in a receiver used in a satellite based positioning system (e.g. GPS). In such systems, data pairs including an incoming value and a "raw" reliability estimate (e.g. a standard deviation) are normally fed directly to the Kalman Filter. The Kalman Filter computes the resultant and an overall uncertainty estimate by applying a "weight" to each successive incoming value based on its reliability. The Kalman Filter also estimates incoming values based on past values.The method involves the unique steps of replacing the raw reliability with a "modified" reliability if the incoming value is too far from the estimate in view of an adjustable limit envelope defined by the current uncertainty estimate and reliability value. If the difference between what we get and what we expect is small, then the reliability value is passed without modification.

Abstract: A system for resynchronizing the timing and carrier phases of a modem receiver signal to enable the receiver to quickly reacquire the timing phase and the carrier phase, and thereby restart the demodulation process. The system provides accurate estimates of the timing and carrier phases, as well as a gain correction factor to provide for proper alignment for decoding. The discrete Fourier transform of the received signal is multiplied by the complex conjugate of the discrete Fourier transform of the transmitted signal to produce estimates of the desired phases. Gain control and carrier phase control are performed to determine corresponding error signals to adapt the resultant estimated timing and carrier phases, and gain correction.

Abstract: A communications detector for detecting remote user hang-up or disconnection by a telephone answering machine (TAM). The remote hang-up detector (RHUD) may operate in conjunction with a modem and does not affect transmission and receipt of modem signals and modem performance. An optically isolated voltage detector indicates to the TAM that the remote user has hung up by detecting reversal or interruption of the loop current supplied by the central office, thereby causing the local user or modem to likewise hang up.

Abstract: A high speed current sense amplifier useful in memory devices, which includes a current-to-voltage amplifier that is coupled to a voltage amplifier. The current-to-voltage amplifier has an input impedance that is lower than its output impedance. The voltage amplifier has an input impedance that is larger than the input impedance of the current-to-voltage amplifier. The current sense amplifier can sense the current relationship between two current inputs in about 200 pico-seconds. Embodiments of the current sense amplifier enable current sensing either near the power supply voltage or near ground, thus eliminating the need for intermediate voltages. Embodiments of the current sense amplifier draw current from the current inputs only during the 200 pico-second sensing time and does not require external latching circuitry.

Abstract: The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.

Abstract: A system and method for generating NTSC and PAL formatted composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components in accordance with NTSC and/or PAL formats. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Alternatively, a pixel clock frequency equal to an integer multiple of the carrier frequency may be used and modulation in accordance with the NTSC and PAL formats may be accomplished by inverting, setting to zero or leaving unmodified the chrominance components. The architecture of this system greatly reduces hardware complexity and bandwidth requirements.

Abstract: Aspects of the present invention provide a system for selectively processing a video signal in accordance with instructions from application software. The system contains a video decoder for converting an analog video signal to digital video data, and a controller for formatting and routing the digital video data. A list of control structures may be loaded into a memory associated with the controller. The control structures contain formatting and routing information used by the controller to process different portions of the video stream. The number and content of control structures as well as the correlation between the control structures and selected portions of the video stream may be flexibly determined by application software. In particular, the control structures may be configured such that certain portions of the video stream are routed to the CPU for processing, while other portions are routed to a display driver and output on a display device.

Abstract: A data access arrangement (DAA) interface for alternately coupling a telephone set to a modem for operation in conjunction with and independent of the central office power supply line. The DAA interface provides an enhanced power supply to supply adequate power to the telephone set when the telephone set, or a computer coupled thereto, communicates with the modem independent of the central office line. Multiple relays are coordinated and controlled via an application program in communication with the modem which detects certain conditions representing incoming and outgoing telephone and data/facsimile calls, and commands the relays to respond to the conditions.

Abstract: A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing.

Abstract: A fault isolation system for use in an integrated circuit. The fault isolation system includes multiple input shift registers which are connected end-to-end, serial output to serial input, for convenient interface with a test data input and test data output that are controlled by the test access port controller (tap controller) of conventional JTAG circuitry that is frequently provided in such integrated circuits. The multiple input shift registers include parallel inputs which receive test data from test nodes within functional blocks such as general circuit blocks and linear bus alleys. The multiple input shift registers are efficiently controlled by a global controller which talks to many local controllers. The global controller distributes control signals that are received by the local controllers.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: A pitch estimation device and method utilizing a multi-resolution approach to estimate a pitch lag value of input speech. The system includes determining the LPC residual of the speech and sampling the LPC residual. A discrete Fourier transform is applied and the result is squared. A lowpass filtering step is carried out and a DFT on the squared amplitude is then performed to transform the LPC residual samples into another domain. An initial pitch lag can then be found with lower resolution. After getting the low-resolution pitch lag estimate, a refinement algorithm is applied to get a higher-resolution pitch lag. The refinement algorithm is based on minimizing the prediction error in the time domain. The refined pitch lag then can be used directly in the speech coding.

Abstract: The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output.

Abstract: A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing.

Abstract: A multi-purpose current source which provides both a PTAT and a constant current source and which requires only one precision external or laser trimmed resistance. The PTAT constant current circuit includes a differential amplifier having one input coupled to a V.sub.PTAT reference voltage and the other input coupled to a V.sub.bg scaling circuit. The tail current for the differential amplifier is held constant at the current level of an associated constant current source based upon V.sub.bg. Therefore, the amount of current output from the PTAT current source will be dependent upon the current of the constant current source, rather than upon a resistance value. By setting the scaling circuit appropriately, the current that flows through the output leg of the differential amplifier in the PTAT current source when the ambient temperature is equal to 25.degree. C. will be equal to one half the tail current through the differential amplifier, and thus one half the current output from the constant current source.

Abstract: A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions.

Abstract: The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention separates a plurality of bits in each digital word into a plurality (e.g. 2) of segments. A first register off the chip latches the first bits in each word with a first clock signal. A second register off the chip latches the second bits in each word with a second clock signal delayed from the first clock signal. The first register bits are latched on the chip with the first clock signal by a third register. The delayed second register bits are latched on the chip by a fourth register with the second clock signal or with a delayed first clock signal having the same delay as the second clock signal. Substrate ties for the third and fourth registers may be connected to at least one, preferably a plurality, of bonding pads on the chip.

Abstract: A testing and evaluation system for efficiently qualifying individual components of a modem. A modem data pump acts as a dBm meter by measuring distortion, noise floor, and echo. The modem is coupled to a computer and a remote modem. After calibration, the remote modem may be disconnected. A resistor having a preselected resistance is coupled to the modem to allow the computer to measure the modem noise floor and distortion independent of particular telephone connections. An echo canceler coupled to the receive line allows the sum distortion and noise to be measured.

Abstract: A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer includes a plurality of circuit blocks each responsive to the binary indications in the lines of an individual one of the buses. Each block has a plurality of recursive circuits each having first and second stages. The second stages of the recursive circuits in an individual one of the circuit blocks receive an individual one of a plurality of control indications at a first side of the block to activate the first stages in such recursive circuits. The first stage in each recursive circuit in each individual circuit block receives at a second side of the block the binary indications in an individual line in an individual one of the buses to obtain a signal from such first stage in accordance with such binary indication upon the activation of such first stage.

Abstract: The present invention relates to circuitry for a receiver having a low cost filter using automatic alignment of the center frequency of signals input to the filter to suppress noise and out-of-band signals from the filter output over a narrow bandwidth. An RF input signal to the receiver is downconverted to an IF frequency using a VCO, and the IF signal is provided to the low cost filter. The output of the filter is input to a frequency correction circuit and a distortion detection circuit. The distortion detection circuit provides an error signal including positive frequency shift errors determined from digital ones identified from the filter output signal, and negative frequency shift error signals determined from digital zeros in the filter output signal.