Abstract: Device, system and method of modification of PCI Express packet digest. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of a digest portion carry non-ECRC data.

Abstract: The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock domains where the fast clock rate is an integer multiple of the slow clock rate by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainty of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.

Abstract: Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

Abstract: Disclosed is method and chaos circuit for a random number generator comprising: a differential sample and hold circuit portion having a first and a second differential signal input and a first and a second differential signal output, a differential non-linear discriminator circuit portion that applies a differential discrimination function upon the first and the second differential signal output and outputs a first and a second discriminated signal, where the first and the second discriminated signals are also coupled to the first and the second differential signal inputs via a first and a second loop feedback.

Abstract: Managing Message Signaled Interrupts (MSIs). For example, a method of managing MSI requests in a computing system may include receiving a plurality of MSI requests from one or more components of the computing system; directing data of the plurality of MSI requests to be stored sequentially, according to a First In First Out (FIFO) order, in successive entries of a FIFO structure defined in a main memory of the computing system; and directing a processor of the computing system to retrieve data of one or more of the plurality of MSI requests from the FIFO structure to be processed according to the FIFO order. Other embodiments are described and claimed.

Abstract: Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.

Abstract: Device, system, and method of utilizing PCI Express packets having modified headers. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of an ID field carry non-ID data.

Abstract: Device, system and method of correcting an integrated circuit design. For example, a method includes receiving a list of one or more root points for an active netlist that requires logic correction, wherein the root points correlate between elements of the active netlist and elements of a re-synthesized netlist that is based on a high-level correction for the integrated circuit design; automatically identifying in the active netlist a driving logic cone for at least one of the root points; and automatically identifying in the re-synthesized netlist a driving logic cone for the respectively correlated root point, including one or more corrected logic elements that correspond to the one or more identified flawed logic elements.

Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.

Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Abstract: A method for tracking pitch signal, including receiving a detected pitch signal that consists of a succession of pitch values, and for each current pitch value in the detected signal perform the following steps: constructing sub-sequences of consistent pitch values from neighboring pitch values. Next, calculating significance of the sub-sequences, and selecting a sub-sequence or a collection of consistent subsequences with highest significance. If the current pitch value is not consistent with the sub-sequence with highest significance, smoothing the current pitch value by diving it or multiplying it by an integer value>1, so as to render it consistent with the sub-sequence with highest significance.

Abstract: A pitch estimation system including a low-frequency band noise detector (LBND) operative to detect the presence of low-frequency band noise in a first audio frame, a frequency-domain pitch estimator operative to calculate a pitch estimation of a second audio frame from at least one spectral peak in the second audio frame, and a pitch estimator controller operative to cause the pitch estimator to exclude from the spectrum of the second audio frame at least one low-frequency spectral peak below a predefined threshold where low-frequency band noise is present in the first audio frame.

Abstract: An inexpensive storage system is disclosed along with methods of managing such a system. In one preferred embodiment, the system includes a high performance high reliability storage medium configured for initial storage of data, a low performance high reliability storage medium configured for backup of data initially stored on the high performance high reliability storage medium, and a high performance low reliability storage medium, configured to receive data transferred from the high performance high reliability storage medium, after the data has been backed up on the low performance high reliability storage medium. This significantly reduces the cost of the system without substantially comprising performance. Reliability is likewise maintained owing to the high reliability backup.