Abstract: Disclosed is a multi-phase power regulator that accurately senses current at a load in a lossless manner and adjusts the power supplied to the load based on the sensed current. Also disclosed is a method of calibrating a multiphase voltage regulator by applying a known calibration current at the load and determining actual current values by the difference in measured values between when the known calibration current is applied and when it is not applied. The accurate current is determined at a known temperature and accurate temperature compensation is provided by a non-linear digital technique. Each phase of the multi-phase power regulator is individually calibrated so that balanced channels provide accurate power to the load. Also disclosed is a calibration method with minimal noise generation.

Abstract: Disclosed is a fine resolution pulse width generator for use in a multiphase pulse width modulated voltage regulator. The fine pulse width is generated by first generating a pulse with a coarse pulse width and one or more delayed replicas thereof. Then, digitally controlled analog interpolators are used to generate the fine resolution pulse width pulse by interpolating among the coarse pulse width pulses. Both single edge and double edge modulation embodiments are disclosed providing interpolation of just the trailing edges of the coarse pulses or both the leading and trailing edges, respectively. The disclosed fine resolution pulse generator uses counters, thermometer encoders and analog interpolators to achieve interpolation accurately by insuring that each interpolation step corresponds to an equal weight. Accuracy of the interpolation is defined by the linearity (i.e. how well the interpolation fits a best fit straight line) and monotonicity (i.e. how each step contributes a positive weight to the total).

Abstract: A highly phased power regulation (converter) system having an improved control feature is provided. A controller, such as a digital signal processor or microprocessor, receives digital information from a plurality of power conversion blocks and transmits control commands in response to the information. The controller is able to change the mode of operation of the system and/or re-phase the power blocks to accommodate a dynamic load requirement, occasions of high transient response or detection of a fault. A compensation block within the controller is used to regulate the output voltage and provide stability to the system. In one embodiment, the controller is implemented as a PID compensator controller. In another embodiment, a microprocessor is able to receive feedback on its own operation thus providing enabling the controller to anticipate and predict conditions by analyzing precursor data.

Abstract: Disclosed is a system and circuit for a multi-channel optoelectronic device driver. The system and circuit include a differential buffer amplifier, an output driver amplifier, a dedicated voltage regulator, a load compensation circuit, a wave shaping circuit and a laser fault detection circuit. In a multi-channel configuration, each channel has a dedicated voltage regulator such that each channel provides a channel-specific drive signal.

Abstract: A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires.

Abstract: An optical coupler for forming an optical connection between one or more two dimensional photonic array devices and an optical fiber and for forming an electrical connection between the two dimensional photonic array devices and a substrate, a system including the optical coupler and materials, and methods of forming the optical coupler and system are disclosed. The optical coupler includes a light transmission medium and electrical connectors, which are at least partially encapsulated. In addition, the device includes alignment guides configured to receive guide pins from a fiber optic connector, such that when the fiber optic connector is attached to the optical coupler, fibers of the ribbon align with the two dimensional photonic array device(s) via the light transmission medium.

Abstract: The method and device according to the present invention provides a control system, method and apparatus for synchronizing a reference signal to high frequency data signals. Pulses are accumulated before reaching the integrator. Pulse accumulation is provided in a DLL clock and data recovery circuit. Pulses are accumulated using a ripple divider for rising transitions only. In another exemplary embodiment, pulses are accumulated using a ripple divider for both rising and falling transitions.

Abstract: A method for converting power includes charging an inductor by coupling the inductor to a voltage source for a predetermined amount of time. Thereafter, the inductor is discharged by coupling the inductor to a ground until the current flowing through the inductor equals zero. A method for detecting a zero current flowing through the inductor includes coupling the inductor to a transistor and comparing the output of that transistor to a transistor coupled to ground.

Abstract: Disclosed is a memory array in which each cell consists of a pair of cross coupled bipolar transistors with antisaturation clamps, a load resistor connected to the collector of each of the cross coupled transistors forming storage nodes, and Schottky barrier diode input/output devices connecting each node to a respective bit line. The emitters of the cross coupled transistors are connected to a lower word line while the load resistors are connected to an upper word line. Both the upper and lower word lines are switchable providing high speed as well as highly stable operation with very low power supply voltage requirements.

Abstract: This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

Abstract: Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary inputs (PI) to the logic network to be tested while the output of several of the logic blocks are also outputs (PO) of the logic network to be tested. However, the inputs and outputs of many logic blocks of the network to be tested are inaccessible since as is well known in large scale integration (LSI), a large number of internal circuit nodes cannot be probed directly. In accordance with the present disclosure, such a logic network to be tested is simulated and each of the logic blocks as well as the inputs and outputs of each of these logic blocks is uniquely defined. A first test pattern is then applied to the primary inputs (PI) of the network to set the logic levels on these primary inputs to known values.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: A square-shaped electron beam is stepped from one predetermined position to another in a line-by-line scan to form a desired pattern on each chip of a semiconductor wafer to which the beam is applied. At each of the predetermined positions, the beam is on, off, or on for a portion of the time period at which the beam is disposed at the predetermined position. The beam also can be offset both along its direction of movement and perpendicular thereto at each of the predetermined positions. Control of this movement of the beam is obtained through utilizing a memory with no change being made in the memory if the predetermined position at the next line does not have any change from the predetermined position at the line along which the beam is moving.