Abstract: This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells.

Abstract: An improved structure and method for fabricating amorphous silicon thin film devices, particularly transistors, is described. In additiion to their usual role as gate insulator and optional capping layer, the insulator films are chosen to maximize the transmission of photolithographic active light through the structure. These layers are positioned to either side of the amorphous silicon layer which is a light absorbing layer to act as anti-reflective elements. The insulator layers are chosen to have a refractive index different than the substrate and a thickness dimension chosen so the wave components of said lithographically active light reflected at the interfaces of the completed structure interfere destructively.

Abstract: A low band gap semiconductor heterostructure having a surface adaptable to planar processing and all semiconductor properties supported by a fabrication constraint relaxing substrate that does not provide a low impedance parallel current path. A superconductor normal superconductor device of n-InAs-100 nanometers thick with niobium superconductor electrodes spaced 250 nanometers apart and a 100 nanometer gate in the space. The N-InAs is supported by an undoped GaAs layer on a semi-insulating GaAs substrate. A heterojunction field effect transistor device having a GaAlAs gate over a channel 100 nanometers thick on an undoped GaAs layer on a semi-insulating GaAs substrate.

Abstract: A color cathode ray tube display includes a degauss coil and a switched mode power supply. The degauss coil is connected in series with the input rectifier (5) of the SMPS to limit the current surge on power on but is shorted out by a switch, preferably constituted by a triac, after the SMPS switching transistor turns on to give substantially zero residual degauss current. Forward voltage drop across the triac can be compensated for by back-to-back diodes (13) connected in series with the degauss coil. The triac is switched under control of a signal from an auxiliary winding on the SMPS output transformer (a).

Abstract: A method is described for depositing thick, low-stress refractory metal films on a substrate. For example, a layer of tungsten of any required thickness may be deposited by the silicon reduction of tungsten hexafluoride in a CVD reactor. This is accomplished by alternating the process step of plasma depositing an amorphous silicon film, with the process step of exposing the silicon film to tungsten hexafluoride until the required thickness of tungsten is reached. The thickness of the deposited amorphous silicon film must be less than the thickness at which the replacement of silicon to tungsten becomes self-limiting to assure that all of the amorphous silicon is replaced. The bombardment of the silicon during plasma deposition "hammers" the underlying tungsten film and relieves the stress in the film.

Abstract: The transistor comprises two electrodes, (source (22) and drain (23), with a semiconductor tunnel channel (21A, 21B) arranged therebetween. A gate (24) for applying control signals is coupled to the channel. The semiconductor channel consists of a plurality of regions differing in their current transfer characteristics: contact regions (21c), connected to the source and drain electrodes, and a tunneling region (21t) arranged between the contact regions. The energy of free carriers in the contact regions differs from the energy of the conduction band or the valence band of the tunneling region which forms a low energy tunnel barrier the height (.DELTA.E) of which can be modified by control signals applied to the gate. The operating temperature of the device is kept sufficiently low to have the tunnel current through the barrier outweigh currents of thermionically excited carriers.

Abstract: A waveform transition sensitive Josephson junction circuit having sense bus and logic applications is disclosed. In a preferred embodiment, a device capable of carrying Josephson current is shunted by a utilization circuit. Current flowing in the device is diverted to the utilization circuit in response to only one of a pair of transitions of a pulsed input applied to the device. On one transition of the applied pulsed input current, a current is induced in a current path which follows the input until the threshold of a switchable device in the current path is exceeded. The switchable device switches and the induced current drops to zero. If the current generated by the transition is in the opposite direction to current in the Josephson device, the Josephson device remains in its unswitched state.