Abstract: A very rapidly converging adaptive filter which uses a variable scale factor for each weight of the filter. The value of the variable scale factor is chosen for each iteration and is based upon the sign changes of the incremental weight change. The variable scale factor exhibits large values when no sign changes occur and smaller values when sign changes occur. The new filter provides considerable improvement in increase of convergence rate and decrease in residual errors even in the presence of heavy noise while requiring only a modest increase in hardware.

Abstract: An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a translate map gate array generates an address to the translate RAM in response to mapped and remapped instructions being fetched from the instruction buffer. The map gate array looks at an operation code included in the instructions and determines if remapping is required. If so, an address is generated including a constant providing a block of specific addresses and a variable providing a specific address within the block. The mapped instruction includes a seven bit operation code field and, in response to a mapped instruction being fetched, all of the seven bits are mapped directly to the translate RAM address.

Abstract: A compensated laser diode transmitter for high speed data transmission is provided with a pair of current switches, a novel current summing circuit and a novel current sink. The power output of the laser is sensed in real data time and employed to generate instantaneous feedback signals capable of instantaneously rebalancing and maintaining the power output of the laser diode.

Abstract: A coherent detection and decoding circuit coherently recovers data embedded in a self-clocking data signal by recovering the clock in one integrate and dump circuit and recovering the data in a second integrate and dump circuit. The two integrate and dump circuits are connected to the source of self-clocking data signal and to one of the outputs from a clock phase select switch which produces an inphase clock signal and a NOT inphase clock signal. The inphase clock signal is connected to the integrate and dump circuit which produces the output data signal and the NOT inphase clock signal is connected to the clock recovery integrate and dump circuit. When the presence of a data pulse is detected in the clock phase detection circuit the output signal is coupled to the clock phase select switch so as to reverse the output clock signals and synchronize the inphase clock signal with the data embedded in the self-clocking data input signal.

Abstract: The present invention is concerned with an apparatus and a method of jumping a composite PN code from a current phase position to a desired predetermined phase position so as to enhance acquisition of a composite PN code. The apparatus includes a plurality of individual PN code generators which are connected to a code combiner to produce a composite PN code. Each of the individual PN code generators is driven by its own timing gate for supplying synchronized clock pulses to its own PN code generator. A master clock is connected to a timing gate before being connected to the individual PN code generators. An inhibit input at each of the individual timing gates is provided so that the individual PN generators may be inhibited a predetermined number of clock pulses which causes the PN code generated to be inhibited and has the effect of jumping the PN code a desired number of phase positions.

Abstract: A planar array of radiating elements which includes a plurality of radiating elements which are capable of operating upon electromagnetic signals of different frequency bands in a single planar array.

Abstract: An ultra high frequency multiplexer for combining very high frequency data inputs to produce multiplexed data outputs in the Gigahertz range is provided. Typical ECL output data pulses from integrated circuits are employed as inputs to individual gates of a plurality of dual gates GaAs MESFETS. The second gate of the individual GaAs device is provided with an ultra high frequency clock enable pulse that produces a plurality of pulses are ultra high frequency pulse rates. The outputs of the GaAs devices are delayed one from the other and the delayed outputs are recombined in a combining network to provide a combined multiplexed data output at ultra high frequency.

Abstract: A CMOS buffer receiver is provided for converting TTL or CMOS input voltage signals to CMOS signals so as to drive CMOS loads on VSLI chips. The buffer receiver comprises a reference voltage generator coupled to a compensation network having an output signal which varies with process, temperature and voltage supply. The compensated output signal is coupled to the gates of any number of current source load transistors of a plurality of series connected transistor pairs which comprise individual stabilized input converters all of which have their switchpoint located in the middle of their characteristic curves so that their switchpoints are immune to process, temperature and supply voltage variations.

Abstract: A long phase-locked loop circuit is provided which has an electronic closure circuit in series in the loop. The loop is effectively an open loop until acquisition of the incoming signal at which time the electronic closure circuit closes the phase-locked loop. A novel coincidence circuit is provided which compares the carrier in the loop with a reference frequency and when the two frequencies are equal the coincidence circuit closes the electronic closure circuit.

Abstract: A novel thin film processing substrate is embodied into a multichip hybrid module. The processing substrate is provided with conductive vias which are arranged in an area array having the same pattern as the lead out pin vias on a base substrate. The top surface of the processing substrate is built up by thin film techniques to provide a laminate thereon comprising a ground plane and a plurality of thin film X-direction and Y-direction signal distribution lines separated one from the other by thin polyimide insulating layers. The interconnecting thin film lines and polyimide layers are built up as patterns using photolithographic techniques. The X and Y-direction conductive lines and the ground plane are selectively interconnected through the vias and each other to form a predetermined signal distribution circuit.

Abstract: An electrically passive keyboard is provided with an array of keys. Each key is provided with an actuating bar which when depressed cooperates with a plurality of coded shutters. Each shutter is arranged to intercept a beam of light passing from light projecting elements to light collecting elements. Light pulses generated at a light source are coupled to the projecting elements with fiber optic cables. Decoding logic is coupled to the light collectors with fiber optic cables. Delay elements are provided in series in the fiber optic cables so that the decoding elements receives a plurality of binary coded light signals in a predetermined timed sequence which are converted into binary coded electrical signals at a point remote from the electrically passive keyboard.