Abstract: Disclosed is a process fo fabrication of a MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicron-wide dummy gate mask consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide laeyr is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region.

Abstract: A hermetic compression sealing system with a semi-conductor, multi-chip thermal conduction module, involving a ceramic substance which includes interconnected semi-conductor chips containing integrated circuits defining the module; an arrangement is provided for directly sealing the module involving a compression seal which is in direct bearing contact with the substrate, a cover in direct bearing contact with the compression seal, and a clamping plate for holding the cover, compression seal and ceramic substrate in sealing arrangement, thereby forming a sealed chamber surrounding the module; a gas charge, such as of helium or the like, within the chamber enables conducting heat from the semi-conductor chips of the ambient.