Abstract: A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of inputs of the test mode data.
Abstract: According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference block. In order to check an operating characteristic of the reference block, a threshold voltage level of the programmed memory cell is read. Parameters for performing an operation of the flash memory device are determined based on the operating characteristic of the reference block. The parameters are stored in the reference block.
Abstract: This invention is based upon the finding that certain chlorosulfonated ?-olefin copolymers can be beneficially utilized in drilling fluids that are utilized in drilling subterreanean wells. For instance, it has been unexpectedly found that certain chlorosulfonated ?-olefin copolymers can be beneficially used as total or partial replacements for organoclays in oil based drilling fluids. The chlorosulfonated a-olefin copolymers that are useful in the practice of this invention are typically chlorosulfonated ethylene/octene copolymers or chlorosulfonated ethylene/butene copolymers. The utilization of chlorosulfonated ?-olefin copolymers in oil-based drilling fluids offers (1) long service life at high operating temperatures, (2) minimal formation damage, (3) improved filtration behavior, and (4) highly effective performance at low viscosifier levels.
Type:
Grant
Filed:
April 2, 2008
Date of Patent:
August 16, 2011
Assignee:
Eliokem S.A.S.
Inventors:
Cecile Mazard, Bertrand Guichard, Andrea Valenti
Abstract: An output driver is applicable to two or more interface standards. The output driver includes a pre-driver configured to generate pull-up control signals and pull-down control signals according to a logic value of data to be output and a target resistance, and adjust slew rates of the pull-up control signals and the pull-down control signals according to operation modes, and a driver configured to output the data in response to the pull-up and pull-down control signals.
Type:
Grant
Filed:
June 30, 2008
Date of Patent:
August 16, 2011
Assignee:
Hynix Semiconductor Inc.
Inventors:
Hyung-Dong Lee, Dong-Hwee Kim, Hwa-Yong Yang
Abstract: A transmitting entity transmits a “base” pilot in each protocol data unit (PDU). A receiving entity is able to derive a sufficiently accurate channel response estimate of a MIMO channel with the base pilot under nominal (or most) channel conditions. The transmitting entity selectively transmits an additional pilot if and as needed, e.g., based on channel conditions and/or other factors. The additional pilot may be adaptively inserted in almost any symbol period in the PDU. The receiving entity is able to derive an improved channel response estimate with the additional pilot. The transmitting entity sends signaling to indicate that additional pilot is being sent. This signaling may be embedded within pilot symbols sent on a set of pilot subbands used for a carrier pilot that is transmitted across most of the PDU. The signaling indicates whether additional pilot is being sent and possibly other pertinent information.
Abstract: A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays of the plurality of memory cell matrixes, m being a bit of addresses, wherein a data access operation is performed on normal memory cells in the normal memory cell arrays as normal word lines corresponding to the normal memory cells are activated in response to the addresses, and additional redundancy memory cell arrays in the plurality of memory cell matrixes, wherein repair-expected memory cells in the normal memory cell arrays are replaced with the additional redundancy memory cell arrays as redundancy word lines corresponding to the additional redundancy memory cells are activated in response to the addresses corresponding to the repair-expected memory cells.
Abstract: An apparatus to detect particulate matter. The apparatus includes a sensor electrode, a shroud, and a heater. The electrode measures a chemical composition within an exhaust stream. The shroud surrounds at least a portion of the sensor electrode, exclusive of a distal end of the sensor electrode exposed to the exhaust stream. The shroud defines an air gap between the sensor electrode and the shroud and an opening toward the distal end of the sensor electrode. The heater is mounted relative to the sensor electrode. The heater burns off particulate matter in the air gap between the sensor electrode and the shroud.
Type:
Grant
Filed:
August 22, 2008
Date of Patent:
August 16, 2011
Assignee:
Board of Regents, University of Texas System
Abstract: An impeller (10) for a cooling fan includes a hub (20) having a circular wall (22) and an annular sidewall (24) extending downwardly from a rim of the circular wall, and a plurality of blades (30) extending radially from the sidewall of the hub. Each of the blades includes a first portion (32) near the hub and a second portion (34) away from the hub, wherein each of the first portions is identical to an adjacent one of the first portions, and each of the second portions is different from an adjacent one of the second portions regarding a height thereof, thereby reducing a noise level of the impeller when the it operates.
Type:
Grant
Filed:
November 15, 2007
Date of Patent:
August 16, 2011
Assignees:
Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
Abstract: A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.
Abstract: During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage.
Abstract: A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern (610, 620). Pairs of nets in the circuit design that are adjacent can be identified (625). Each type of bridge fault for which each pair is tested can be determined according to the simulation results (640, 645, 655, 660). A measure of bridge fault coverage for the test pattern can be calculated according to which types of bridge faults each pair is tested and which net of each pair acts as an aggressor for each type of bridge fault tested (675). The measure of bridge fault coverage can be output (680).
Abstract: A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.
Type:
Grant
Filed:
November 25, 2008
Date of Patent:
August 16, 2011
Assignee:
Hynix Semiconductor Inc.
Inventors:
Kyung-Hoon Kim, Sang-Sic Yoon, Bo-Kyeom Kim
Abstract: Acyclic polyaldehydes and polyalcohols having 11, 16 or 21 carbon atoms and comprising at least two aldehyde or hydroxyl alcohol groups, at least three branches, and three or less carbon-carbon double bonds.
Type:
Grant
Filed:
September 22, 2009
Date of Patent:
August 9, 2011
Assignee:
The Procter & Gamble Company
Inventors:
Jeffrey John Scheibel, Robert Edward Shumate
Abstract: A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.
Abstract: A spinnable rotor for a high speed centrifuge includes a housing which defines a chamber interiorly thereof for receiving a whole blood sample and for containing a predetermined amount of red blood cell absorbent gel. The housing includes an upper portion and a bottom portion, the upper portion having a port formed through the thickness thereof. The upper portion has at least a portion thereof formed from a light transmissible material. A light pipe is joined to the upper portion and light transmissively communicates with the light transmissive portion of the upper portion. The light pipe extends at least partially into the chamber and has an open, lower free end. When whole blood filling the rotor chamber contacts the lower free end of the light pipe, the red color of the blood is transmissively communicated to the upper portion of the rotor housing where it is viewable by the user of the centrifuge.
Abstract: An exemplary method of making an FPC includes forming a substrate comprising metal foil layers interleaved with intervening layers by: (a) laminating intervening layers with metal foil layers; (b) adhering a covering film to outermost surfaces of the substrate; (c) defining a hole in one side of the substrate through the covering film and at least two metal foil layers and the intervening layer between the at least two metal foil layers by etching or laser technology; and (d) plating a portion of an inner wall of the hole with conductive material to form a via to electrically connect the at least two metal foil layers.
Abstract: A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same timing, to data lines at mutually different timings, and a data writing unit configured to synchronize the first data and the second data having been transmitted through the data lines and to write the synchronized data in a memory area.
Abstract: A duty cycle corrector includes a delay unit configured to adjust an input clock and an inverted input clock with a delay value controlled in response to one or more control signals and to generate a positive clock and a negative clock, and a duty detector configured to receive the positive clock and the negative clock, to detect duty ratios of the positive clock and the negative clock and to generate the one or more control signals.
Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
Abstract: A positioning mechanism (100) configured for positioning a keypad (20) on a portable electronic device includes a plurality of retainers (10). Each retainer includes a main portion (11) and a fixing unit (12) formed on the main portion. The main portion includes an engaging surface (112) and an opposite latching surface (114). A protrusion (1121) is formed on the engaging surface, a first positioning surface (1122) corresponding to a first portable electronic device (30) is formed on the protrusion. The retainer is mounted to the keypad via the fixing unit.
Type:
Grant
Filed:
December 27, 2007
Date of Patent:
August 9, 2011
Assignees:
Shenzhen Futaihong Precision Industry Co., Ltd., FIH (Hong Kong) Limited
Inventors:
Xu-Ri Zhang, Zheng-Fang Wen, Ye Liu, Rui-Hao Chen