Abstract: A method and system for automatic bad pixel correction in image sensors is provided. The process includes identifying outlier pixels, identifying bad pixels, and performing bad pixel correction. Bad pixels are identified by comparing pixels in a single row or more than one row. A bad pixel value is replaced by a pixel value that depends on the pixel value of non-bad pixels located next to the bad pixel. The system includes means for identifying outlier pixels, means for identifying bad pixels, and means for performing bad pixel correction.

Abstract: A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. Also provided is a data packet format for transferring data, which comprises of an Endpoint Transfer Descriptor (“ETD”) that includes an EndPoint Descriptor and a Transfer Descriptor, wherein the host system programs the parameters of a communication channel for a particular Endpoint. Also included is a technique for partitioning a memory storage device into a first memory buffer and a second memory buffer; wherein the size of the first and second memory buffer may be programmed by the host system and the first and/or second memory buffer may contain more than one USB packet.

Abstract: An expander coupled between at least a first and second SCSI device for transmitting data and training patterns is provided. The expander includes, a first detection module for detecting a training pattern received from the first device; a second detection module that detects when a first section of the training pattern has been transmitted to the second device; and means for changing the expander's mode from a training mode to a repeat mode after the first section.

Abstract: A process and system is provided for setting up a polling interval for a device that sends a not acknowledged (NAK) signal. The process determines the number of times the device sends a NAK signal before a successful data transfer; and also determines a statistical parameter based on the number of times the NAK signal is received before a successful data transfer; and sets a polling interval for the device based on the statistical parameter. The statistical parameter may be an average, median, maximum or minimum number of times the NAK signal is received before successful data transfer. A polling interval may also be set based upon the number times the NAK signal is received, wherein the polling interval increases with the number of NAK signals. The polling interval may double after every NAK signal.

Abstract: An analog to digital converter (“ADC”) is provided that can be used in a system with an internal or external CPU or in an ASIC. The ADC includes a band gap reference (BGR) circuit whose output is internally coupled to an analog input of the ADC; and a positive analog supply voltage (AVDD) and a positive analog reference voltage (REFP) operationally coupled to a same voltage supply; wherein a BGR value is used by a CPU as a calibration constant for determining an AVDD value, a REFP value, and a Bit Weight value.

Abstract: A method and system for determining the location of plural devices operationally coupled to a computer system using a 1-Wire bus is provided. The method includes, determining if more than one bus-coupler is detected by the computer system; disconnecting bus-couplers in an arbitrary manner until a pre-determined number of bus-coupler(s) is visible to the computing system; determining the location of the detected pre-determined number of bus-couplers; storing the location of the detected pre-determined number of bus-couplers; and repeating the foregoing steps until all the bus-coupler locations are determined and stored. The pre-determined number of bus-couplers may be one and the plural devices include switches and analog/digital converters.

Abstract: In a controller integrated circuit, which controls the operation of a peripheral storage device, a transfer monitoring circuit that facilitates the monitoring of successful transfers from outside the controller integrated circuit. The circuit includes a counter circuit that counts the number of successful transfers, a value storing register, a comparison circuit to compare the counter value to the value stored in the register and generate a result. The transfer monitoring circuit speeds up the operation of the controller integrated circuit especially during recovery from error conditions. The monitoring circuit also allows for a more optimal use of a look-ahead cache.

Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.