Patents Represented by Attorney Teradyne Legal Department
-
Patent number: 6826258Abstract: A system and method for testing lines in a network. The system and method are described in connection with a system for use with a telephone network to aid a network operator determine whether the any line can support high speed data services. According to the method, a mapping is created between low frequency measurements and average loop loss over a high frequency range. The average loop loss is sued to compute the equivalent working length of a line, which is an industry standard measure of the ability of a line to support high speed data services.Type: GrantFiled: June 20, 2002Date of Patent: November 30, 2004Assignee: Teradyne, Inc.Inventor: Muhammad A. Afzal
-
Patent number: 6823479Abstract: A testing tool for Internet Service Provider (ISP) network engineers which is used to diagnose network faults, characterize network performance and evaluate new equipment and software releases. The tool can be used to schedule and run proactive tests to identify network problems before subscribers are affected. Further, the tool can be used to provide testing on demand to quickly isolate the root cause of a problem identified by the tool or by network management systems or subscribers. The tool is topology independent and thus does not have to be reconfigured as the network changes. The tool only sends traffic as directed by the network engineer and thus does not generate undesirable heavy network traffic loads, unless such a heavy network loads are desired by the network engineer.Type: GrantFiled: February 14, 2000Date of Patent: November 23, 2004Assignee: Teradyne, Inc.Inventors: Robert E. McElhaney, Jr., David Kaffine, Anthony C. Hughes, William Minckler, Neelesh Agrawal, Peter H. Schmidt
-
Patent number: 6822498Abstract: A clock system for providing a high-speed clock signal to a plurality of integrated circuits is disclosed. The clock system includes an analog signal generator for producing a periodic analog signal of a predetermined frequency and fanout circuitry. The fanout circuitry is coupled to the analog signal generator and includes a transmission line and an RF coupler. The system further includes a plurality of receivers. Each receiver has reference signal input circuitry and clock signal input circuitry. Both the reference signal circuitry and the clock signal circuitry are receptive to coupling locally generated common mode noise. The clock signal circuitry is disposed proximate the RF coupler to provide an RF coupling therebetween.Type: GrantFiled: June 12, 2003Date of Patent: November 23, 2004Assignee: Teradyne, Inc.Inventors: Duane A. Schroeder, Jack Kretchmer, Jacob A. Salmi
-
Patent number: 6819155Abstract: A duty cycle correction circuit for changing the duty cycle for a differential periodic signal is disclosed. The duty cycle correction circuit includes input circuitry for receiving a first differential signal. The differential signal exhibits a first signal component and a complement signal component, each of the components having initial high and low signal levels and respective first and second DC bias levels. The input circuitry includes a differential output having a first path for propagating the first signal component and a second path for propagating the complement signal component. Programmable load circuitry couples to the differential output and includes a programmable input. The load circuitry operates to programmably vary the DC bias level of at least one of the signal components. A differential gain amplifier is coupled to the first differential output and disposed downstream of the load circuitry.Type: GrantFiled: June 23, 2003Date of Patent: November 16, 2004Assignee: Teradyne, Inc.Inventors: Kuok Ling, Martin Kulas
-
Patent number: 6814619Abstract: In one embodiment of the invention, there is disclosed an electrical connector connectable to a printed circuit board on one end, which includes an insulative housing and a plurality of insulative posts disposed in the insulative housing, with the insulative posts arranged in at least one row. Each of the insulative posts has a first side and a second side, and the insulative posts extend in a direction away from the printed circuit board. A plurality of signal conductors are provided, with each signal conductor having a first contact end connectable to the printed circuit board, a second contact end, and an intermediate portion therebetween that is disposed in the insulative housing, wherein the signal conductors are disposed along the first side of the insulative posts.Type: GrantFiled: June 26, 2003Date of Patent: November 9, 2004Assignee: Teradyne, Inc.Inventors: Philip T. Stokoe, Neil J. Bacon, Jason J. Payne, Huilin Ren
-
Patent number: 6786771Abstract: An interconnection system is described. Absorptive material is selectively positioned throughout the system to improve the high frequency performance of the system. Various embodiments are illustrated, including a backplane-daughtercard connector and a printed circuit board.Type: GrantFiled: December 20, 2002Date of Patent: September 7, 2004Assignee: Teradyne, Inc.Inventor: Mark W. Gailus
-
Patent number: 6784679Abstract: A probe tower for an automatic test system includes an insulative retainer for holding an array of differential probe assemblies. Each differential probe assembly is an elongated structure having first and second ends and first and second coaxial portions. Each coaxial portion includes an outer conductor and a pair of annular insulators positioned therein for holding a center conductor. First and second contact pins extend from the center conductor at the first and second ends, respectively. First and second ground pins, which are electrically connected to the outer conductors of the first and second coaxial portions, extend from the first and second ends for conveying ground connections.Type: GrantFiled: September 30, 2002Date of Patent: August 31, 2004Assignee: Teradyne, Inc.Inventors: Charles M. Sweet, Cameron D. Dryden, David W. Lewinnek
-
Patent number: 6784819Abstract: A technique for deskewing digitizer channels in an automatic test system includes applying a waveform of known frequency to the input of each digitizer channel. Each digitizer channel samples the waveform to produce a respective data record. A Discrete Fourier Transform (DFT), or a portion thereof, is then taken for each data record to determine, at minimum, the phase of the waveform. Phase differences across different digitizer channels are converted to time differences, which values are applied to subsequent digitizer measurements to correct for timing skew. Because a large number of samples in a digitizer's data record contribute to the computed phase of the waveform, the effects of timing jitter are substantially eliminated from skew measurements, without the need for repeating measurements and explicitly averaging results.Type: GrantFiled: June 27, 2002Date of Patent: August 31, 2004Assignee: Teradyne, Inc.Inventor: Ka Ho Colin Chow
-
Patent number: 6775628Abstract: A technique for determining the characteristics of an oscillatory test signal includes acquiring a plurality of consecutive samples of a test signal. The samples are mathematically fit to a sinusoidal model, which specifies a plurality of equations. The equations have unknowns that represent characteristics of a sinusoid that substantially intersects the plurality of samples. Solving the equations for the unknowns reveals the test signal's short-term characteristics.Type: GrantFiled: November 27, 2001Date of Patent: August 10, 2004Assignee: Teradyne, Inc.Inventor: Gregory E. Dionne
-
Patent number: 6769935Abstract: An electrical connector assembly suitable for use in a matrix assembly. The electrical connector assembly has two connectors, each assembled from wafers. The individual wafers are sheilded and separate shield pieces are positioned in one connector transverse to the wafers in that connector. Additionally, wafers in at least one of the connectors includes a compliant portion that allows the two connectors to be self-aligning.Type: GrantFiled: February 1, 2002Date of Patent: August 3, 2004Assignee: Teradyne, Inc.Inventors: Philip T. Stokoe, Thomas S. Cohen
-
Patent number: 6768331Abstract: A contact housing adapted for carrying a plurality of compliant contacts is described. The contact housing is for use in contacting a semiconductor wafer-level package having an array of contacts disposed in a predetermined pattern. The contact housing includes a first guide plate formed from a material having a temperature coefficient of expansion approximating that of the semiconductor wafer-level package. The guide plate has a first pattern of apertures formed by a microelectromechanical process such that the pattern of apertures matches the predetermined pattern of contacts on the wafer-level package. A second guide plate is formed similar to the first guide plate, and includes a second pattern of apertures disposed in vertical registration with the first pattern of apertures. A spacer is interposed between the first and second guide plates. The first and second guide plates cooperate with the spacer to form respective receptacles adapted for carrying the plurality of compliant contacts.Type: GrantFiled: April 16, 2002Date of Patent: July 27, 2004Assignee: Teradyne, Inc.Inventors: Simon Longson, Alex Slocum
-
Patent number: 6766411Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.Type: GrantFiled: June 12, 2002Date of Patent: July 20, 2004Assignee: Teradyne, Inc.Inventor: Nathan L. Goldshlag
-
Patent number: 6717432Abstract: A semiconductor test system that includes a tester, a material handling unit and a manipulator that positions the tester relative to the material handling unit. The manipulator is in the form of a cart that can be wheeled to the material handling unit. The cart is attached to the mateiral handling unit to provide course positioning of the tester relative to the handling unit. Major motion of the test head is constrained to an axis perpendicular to the mating interface of the material handling unit. However, compliant motion, with up to six degrees of freedom, is possible in a complaint zone near the handler. In this way, alignment units on the tester and material handling unit can accurately control the final positioning of the tester relative to the material handling unit.Type: GrantFiled: June 17, 2002Date of Patent: April 6, 2004Assignee: Teradyne, Inc.Inventors: Michael A. Chiu, Neil R. Bentley
-
Patent number: 6249128Abstract: An automatic test system for microwave components. The test system includes internally switchable calibration references. As part of a calibration routine, incident power from a source is measured. During the measurement, calibration references are switched to change the amount of power reflected back to the source. Changes in the incident power are measured continuously while this change occurs. The resulting measurements allow the source match term to be determined. Correction is made to the source amplitude to adjust for the source match.Type: GrantFiled: October 22, 1997Date of Patent: June 19, 2001Assignee: Teradyne, Inc.Inventor: Matthew Thomas Begg
-
Patent number: 6222630Abstract: A system for inspecting potentially warped printed circuit board assemblies is disclosed. The system includes an inspection head with an axial, centrally located camera, and a laser disposed at an angle off the central axis. The central camera and the angled laser can be used during an initial scan of a printed circuit board assembly to measure and compensate for warp in the assembly, thereby making a subsequent inspection of the assembly more accurate.Type: GrantFiled: August 26, 1998Date of Patent: April 24, 2001Assignee: Teradyne, Inc.Inventor: Harold Wasserman
-
Patent number: 6173071Abstract: An apparatus and method for inspecting a printed circuit board, whereby a list of windows encompassing respective regions of the printed circuit board are generated. The windows are then scanned, and data representing the respective regions is captured and stored. The captured data includes data relating to a plurality of pixels for each window. Next, data relating to a plurality of adjacent pixels is retrieved, and values of the adjacent pixels are summed. Finally, either the data relating to the plurality of adjacent pixels or the sum of adjacent pixel values is selected for use in subsequent processing. The apparatus and method is especially useful for determining an average brightness level for each window.Type: GrantFiled: December 16, 1997Date of Patent: January 9, 2001Inventors: Harold Wasserman, Gregg E. Fuhriman
-
Patent number: 6037787Abstract: A probe interface device is disclosed that includes a plurality of coaxial contact probe assemblies disposed in an insulative base. Each coaxial contact probe assembly includes a solid tubular shield with a coaxial signal contact probe, which is isolated from the shield by an insulative retainer; and, a solid tubular reference with another coaxial contact probe. The shield and the reference are soldered together at their respective ends. Further, the insulative base includes an upper retainer and a lower retainer attached to a hollow frame. The upper and lower retainers are provided with the same number of holes for engaging a plurality of coaxial contact probe assemblies. The probe interface device can be used for testing mixed-signal devices and is easy to manufacture.Type: GrantFiled: March 24, 1998Date of Patent: March 14, 2000Assignee: Teradyne, Inc.Inventor: Arthur E. Corwith