Abstract: A system for controlling a relative length a first optical fiber and a second optical fiber includes a first heater coupled to the first optical fiber, a second heater coupled to the second optical fiber, and a controller coupled to the first heater and the second heater. The controller operates the first heater in response to a temperature less than a predetermined temperature and operates the second heater in response to the temperature greater than the predetermined temperature. This allows the length of the optical fibers to be maintained evenly.

Abstract: In bonding a number of pads which may have different heights within a predetermined tolerance the bonding tool (28, 24, 14, 10) is moved in slow speed search mode (70) to contact the first pad (P.sub.1) and store the height (H.sub.1) of the first pad (P.sub.1). After a predetermined amount of continued overtravel (OT.sub.1) the bond is performed and the tool raised. Operations on other pads may occur at this point. The tool is then moved to a point above the location of the second pad. The tool is moved down to the second pad without a search mode but to a second pad target height (H.sub.1 +OT.sub.2) that is the sum of the sensed height of the preceding pad and an overtravel distance.

Abstract: A radiation hard, high voltage integrated circuit device fabrication process. A silicon substrate is implanted with ions that form a buried layer and an epitaxial layer of silicon is grown thereover. The structure is heated to form adjacent N- and P-channel regions. Channel stops are then formed surrounding the respective channel regions. After forming the channel stops, the substrate is masked and predefined dopant ions are implanted into the source and drain regions of the respective wells in the substrate. The distribution of the dopant ions therein are adjusted to have a predetermined doping profile that defines a graded junction. Then the substrate is heated to a relatively high temperature to provide a high temperature drive cycle that forms a desired graded junction profile. A field oxide layer is then deposited on the substrate, and it is masked and etched to define active areas. A gate oxide layer is grown on the substrate above the active areas, and polysilicon gates are formed thereon.