Abstract: A method for making an asymmetric MOS device having a notched gate oxide wherein a region of the gate oxide adjacent to either the source or drain is thinner than the remainder of the gate oxide. The resulting MOS device includes a channel under the notched region of the gate oxide with a relatively high concentration of mobile charge carriers.

Abstract: A method for generating the sticky-bit includes encoding the first operand to represent the number of trailing zeros in the first operand. Then the second operand is encoded to represent the number of trailing zeros in the second operand. The encoded values are then added together to form a sum representing the number of trailing zeros in the multiplication result. The sum total number of trailing zeros is then compared to a predetermined constant. The constant is equal to the number of bits used in determining the sticky-bit. If the sum is larger than the constant, then the sticky-bit is given a value of zero and, conversely, if the sum is smaller than the constant, the sticky-bit is given a value of one.

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505. . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .

Abstract: A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus starts a memory read transaction, the host converts the virtual address of the memory read transaction to a physical address. The snoop logic circuit checks to see whether the physical address is in the bus cache and, if so, whether the data in the bus cache corresponding to address is valid. If there is a bus cache hit, the corresponding data is accessed from the bus cache and output onto the peripheral bus.

Abstract: A circuit for generating the sticky-bit includes a first encoder, a second encoder and an adder circuit. The first and second encoders respectively provide encoded values representing the number of trailing zeros in the first and second operands of the multiplication operation. The adder receives the encoded values from the encoders and a constant. The constant represents the number of bits used in determining the sticky-bit. The adder circuit then adds the encoded values together to generate a sum representing the number of trailing zeros in the resultant. The adder circuit then compares the sum to the constant. If the sum is larger than the constant, then the sticky-bit is given a value of zero and, conversely, if the sum is smaller than the constant, the sticky-bit is given a value of one.

Abstract: A PCI-to-PCI bridge circuit configurable to pass a parity error from one bus to the other bus during a prefetch includes a first interface for interfacing with a first PCI bus, a second interface for interfacing with to a second PCI bus, and a parity correction logic circuit. In response to one of a set of predetermined read commands from a device on the first PCI bus to read data from a device on the second PCI bus, the bridge circuit will initiate a prefetch transaction on the second PCI bus to read the requested data from the device on the second PCI bus. The parity correction logic circuit is coupled to receive from the first interface a first byte enable signal and a second byte enable signal, which are part of the read transaction on the first PCI bus. The parity correction logic circuit is also coupled to receive from the second interface a parity signal corresponding to the prefetch transaction on the second PCI bus.

Abstract: Circuits and methods of suppressing noise on a signal line are disclosed. A noise suppression pull-down circuit is coupled to a signal line which couples the output element of a first logic element to the input terminal of a second logic element. When the first logic element drives a logic low onto the signal line, the noise suppression pull-down circuit is activated to provide a weak pull-down on the signal line. When the first logic element drives a logic high onto the signal line, the noise suppression pull-down circuit is deactivated to prevent interference with the first logic element.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a buffer block containing one or more nth-level buffers implemented with predefined modular buffers. The logic block includes one or more predefined areas containing clocked logic elements. The number of clocked logic elements in a predefined area is constrained to be less than or equal to a predetermined maximum number. Each nth-level buffer receives the clock signal outputted by the external buffer and distributes this clock signal to the clocked logic elements within a corresponding predefined area of the logic block. The nth-level buffer driving each predefined area is implemented by selecting one or more buffers from a family of predefined modular buffers appropriate for the number of clocked logic elements in the predefined area.

Abstract: Certain bits in existing op code formats for a processor do not change from one instruction to another when particular classes of instructions are used. Applicants optionally utilize one or more of these bits to identify one of a plurality of different register files from which to retrieve operands or to store the results of an operation. These bits along with allocated address bits in predetermined address fields now allow the processor to address many more registers. This can be used to increase the performance of the processor. Those programs not utilizing the bits outside of the address fields for designating a particular register file are backwards compatible with the modified processor.