Abstract: A method for compensating for bit line delays in semiconductor memories including the steps of developing a dummy word line signal representative of the delay of a word line of a semiconductor memory and controlling the sense amplifier of the semiconductor memory with a control signal derived, at least in part, from the dummy word line signal. Preferably, the dummy word line signal is delayed by a fixed delay or by delay produced by a proportionally loaded dummy bit line. A circuit embodying the method of the present invention includes a dummy word which produces a dummy word signal upon the activation of any word of the semiconductor memory and a delay coupling the dummy word signal to the clock input of the sense amplifier. The delay may be a fixed delay including a number of logic elements, or it may be developed by a proportionally loaded bit line which has a fraction of the load of an actual bit line of the semiconductor memory.

Abstract: A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.

Abstract: A differential output buffer formed on a monolithic semiconductor substrate characterized by a bias generator coupled to a voltage source and a output stage coupled to the bias generator. The bias generator develops a bias output having a voltage level less than that of the voltage source. The output stage is responsive to a pair of complementary CMOS logic level inputs and uses the bias output of the bias generator to develop a pair of corresponding, low voltage swing outputs. In one embodiment the bias generator and the output stage operate in an open-loop and produce output signals which swing approximately two volts and in another embodiment the bias generator and the output stage operate in a closed-loop configuration and produce output signals which swing approximately one volt.

Abstract: A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.

Abstract: A digital output buffer including a driver capable of driving an output signal up to a maximum drive level and a driver controller responsive to contention at the driver's output and operative to reduce the drive of the driver below the maximum drive level when contention is detected. The method for reducing contention at the output of a digital buffer includes the steps of sensing the desired output of a digital buffer, sensing the actual state at an output node of the digital buffer and reducing the output drive of the digital buffer when the desired output is in contention with the actual state at the output node.

Abstract: A method for detecting imminent end-point when plasma etching a dielectric layer of a substrate by monitoring the D.C. bias voltage of the cathode during the etching process. The D.C. bias voltage gives an indirect reading of the impedance of the substrate which changes appreciably just prior to etch-through of the dielectric layer. The plasma etching process is then terminated and a less damaging etch process is used to complete the etch-through of the dielectric layer. The apparatus of the present invention includes an A.C. blocking network coupled to the cathode, an A/D converter coupled to the blocking network and a digital signal analyzer coupled to the A/D converter. Plasma etching can be automatically terminated by the signal analyzer upon the detection of imminent end-point.

Abstract: Circuitry within a device provides an output signal to an output pad of the device. One of a plurality of current levels is selected. When a first current level is selected, the circuitry generates only a first amount of current to maintain the output signal on the output pad. When a second current level is selected, the circuitry, in addition to the first amount of current, generates a second amount of current to maintain the output signal on the output pad. The first current level may be used in a test mode. In this way high current switching noise can be eliminated during testing. The second current level may then be used in a normal operating mode.