Abstract: An automated method for provisioning a grid used to run a load test on a target website includes sending one or more requests in a multi-threaded manner to at least one cloud provider, the one or more requests for an allocation of N load server instances and M result server instances which comprise the grid. Requests received back from the cloud provider are also handled in a multi-threaded manner; any errors occurring during the allocation being corrected automatically. The N load server instances and the M result server instances are then verified to be operational and correctly running software deployed to provide defined test services. Errors identified during the verification are automatically corrected either by attempting to restart a failed instance or allocating a different instance.

Abstract: A method of operation for flyback power converter includes operating a controller of the flyback power converter in a regulation mode when a control signal is below a first threshold. The control signal is provided as an input to a terminal of the flyback power converter. When the control signal is below a second threshold and above the first threshold, the controller is operated in a limiting mode. The controller is operated in an external command mode when the control signal is below a third threshold and above the second threshold. Lastly, when the control signal is above the third threshold, the controller is operated in a protection mode.

Abstract: In one embodiment, a graphical user interface (“GUI”) enables the efficient composition and execution of a test of a message-based application, Web application, or SOA systems' capacity to receive, process and respond to message traffic. The GUI may be used to generate a test composition by dragging and dropping message clips onto one or more tracks. Each clip includes one or more message, with each track being organized into one or more bands. Each track and each band may run contemporaneously to send messages to a target device or application. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

Abstract: A video repository unit includes a plurality of disk drives arranged in a redundant array and circuitry to control writing/reading of video programs to/from the redundant array. A wireless transceiver receives video programs and transmits a selected video program to a remote viewer responsive to a request received by the wireless transceiver. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.

Abstract: A package includes a body that encapsulates a semiconductor die, the body having a first pair of opposing lateral sides, a second pair of opposing lateral sides, a top, and a bottom. The bottom has a primary surface and a plurality of protrusions that extend outward from the primary surface. When the package is mounted to a printed circuit board (PCB) the protrusions contact the PCB and the primary surface is disposed a first distance away from the PCB. The package further includes a plurality of leads that extend outward from the first pair of opposing lateral sides.

Abstract: In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.

Abstract: A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.

Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.

Abstract: In one embodiment, a method includes sending, from an originating gateway device (OGW) to a terminating gateway device (TGW), a setup message for setting up a call on a primary bearer channel (B-channel) of an Integrated Services Digital Network (ISDN). The OGW interconnects with a first Internet Protocol (IP) video endpoint, and the TGW interconnects with a second IP video endpoint. In response to an alerting message sent from the TGW, the OGW initiates procedures for synchronizing a plurality of secondary B-channels between the OGW and the TGW prior to the call entering into a connect state. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract: A network for wireless transmission of a media data in a building includes a plurality of access points. A first access point receives the media data from a source and transmits the media data downstream at a first data rate. A plurality of additional access points is distributed about the building, each of which includes an upstream transceiver to receive the media content on a first channel and a downstream transceiver to re-transmit the media content at substantially the first data rate on a second channel. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A network for wireless transmission of a media data in a building includes a plurality of access points. A first access point receives the media data from a source and transmits the media data downstream at a first data rate. A plurality of additional access points is distributed about the building, each of which includes an upstream transceiver to receive the media content on a first channel and a downstream transceiver to re-transmit the media content at substantially the first data rate on a second channel. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.

Abstract: A Service Provider (SP) authentication method includes receiving a message from a subscriber-premises device, the message being compatible with an authentication protocol and being transported from the subscriber-premises device to a u-PE device operating in compliance with an IEEE 802.1x compatible protocol. Access to the SP network is either allowed or denied access based on a logical identifier contained in the message. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).