Abstract: A four-transistor RAM cell is provided by a pair of cross-coupled driver transistors configured to store a data value, and a pair of access transistors coupled to the driver transistors. The driver transistors and access transistors are sized so the driver transistors are not stronger than the access transistors. In one embodiment, the driver transistors are PMOS transistors and the access transistors are NMOS transistors, with these transistors all having substantially the same size. These PMOS and NMOS transistors are fabricated using a conventional ASIC or logic process. The PMOS transistors are located in an N-well, which is biased at a voltage greater than the VCC supply voltage. The gates of the access transistors are coupled to a word line, and the sources of the access transistors are coupled to a pair of bit lines. The bit lines are coupled a regenerative sense amplifier and a bit line equalization circuit.

Abstract: A memory array requiring periodic refresh operations is controlled such that the refresh operations do not require explicit control signaling or handshake communication between the memory array and a memory controller. External accesses and refresh operations are handled such that refresh operations do not interfere with external accesses under any conditions. A multi-bank refresh scheme reduces the number of collisions between refresh operations and external accesses. A read buffer is used to buffer read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. The memory array, read buffer and write buffer can be constructed of DRAM cells.

Abstract: A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value.

Abstract: A method is provided for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to a source of a neighbor non-volatile memory transistor. The method includes the steps of (1) applying a read voltage to the gates of the first and neighbor non-volatile memory transistors, (2) applying a source voltage (Vs) to a source of the first non-volatile memory transistor, (3) applying a drain voltage (Vd) to the drain of the first non-volatile memory transistor and the source of the neighbor non-volatile memory transistor, and (4) applying a forcing voltage (Vf) to a drain of the neighbor non-volatile memory transistor. In a particular embodiment, the drain voltage Vd is equal to the forcing voltage Vf. Another embodiment includes the step of applying a second forcing voltage (Vfs) to the source of another neighbor non-volatile memory transistor.

Abstract: A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the substrate. A first impurity is implanted into the bit line regions of the substrate, wherein the first impurity is implanted through the ONO layer, through the openings of the mask. The first impurity is implanted at various angles, such that the first impurity is implanted in the substrate at locations beneath the mask. The upper oxide and nitride layers of the ONO layer are subsequently etched through the mask openings. A second impurity is implanted in the substrate through the openings of the mask. The mask is removed, and the substrate is oxidized, thereby forming bit line oxide regions over the bit line regions, and floating gate structures.

Abstract: Five architectures for the implementation of virtual ground non-volatile content-addressable memory are provided. Three of the architectures are applicable to 2-bit non-volatile memory transistors having separate programming capability for two current directions (i.e., drain-to-source and source-to-drain. Another architecture is applicable to any floating gate memory transistor, including 1-bit and 2-bit non-volatile memory transistors. In general, an array of non-volatile memory transistors is arranged in a plurality of horizontal rows and vertical columns. Words are stored in selected columns of the array. Horizontal compare lines are coupled to receive a comparand word, with each compare line being coupled to the gates of the memory transistors in a row of the array. The vertically aligned source/drain regions of the memory transistors are coupled to form word lines. Sense amplifiers are coupled to selected word lines.

Abstract: A semi-conductor memory device having a wide write data bandwidth is provided with high speed read-write circuitry having data amplifiers that are activated to accelerate amplification of write data signals being driven by write data drivers onto data lines of the cell array of the device during memory write cycles, as well as activated to amplify read data signals on the data lines during memory read cycles. Moreover, the data amplifiers are activated in a self-timed manner. In one embodiment, the device is further provided with a read data buffer that is constituted with a regenerative latch and an input stage, and a write data buffer having multiple entries. The input stage of the read data buffer isolates or couples the regenerative latch to the data lines depending on whether the data lines are in a pre-charged state or not.

Abstract: A memory system including a DRAM array, a read buffer, a write buffer and an input/output (I/O) interface. The read buffer and write buffer are coupled between the DRAM array and the I/O interface. When an external transaction involves multiple pieces of data in consecutive address locations, such as a burst access, parallel operations are performed in the DRAM array and the I/O interface. In a burst read transaction, all the data in the burst transaction is pre-fetched from the DRAM memory into the read buffer in one memory cycle. After the read data has been pre-fetched, the DRAM array is available for a refresh operation. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/O interface. In a burst write transaction, multiple burst write data values are written to the write buffer over multiple I/O cycles. This burst write data is not retired to the DRAM array until the next write transaction.

Abstract: A structure and method for configuring an EEPROM having an array of 2-bit non-volatile memory transistors to perform either in a high-speed 1-bit operation mode or a high-density 2-bit operation mode. Each memory transistor has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The selected operation mode is determined by configuration data set by the EEPROM manufacturer in accordance with a customer's requirements. In one embodiment, an EEPROM includes blocks of memory cells accessed by a single word line. When the configuration data indicates the 1-bit operation mode, the memory control circuit stores data in only one of the two charge trapping regions of each memory cell. All eight bits of a word are read simultaneously by accessing eight separate charge trapping regions. Conversely, when the configuration data indicates the 2-bit operation mode, the memory control circuit stores data in both charge trapping regions of each memory cell.

Abstract: A method and apparatus for handling the refresh of a DRAM array so that the refresh has no effect on the external access. This allows an SRAM compatible memory to be built from DRAM (or 1-Transistor) cells. By utilizing the unused external access time for performing the infrequent memory refresh, there is no penalty on the peak bandwidth requirement of the memory array.