Patents Represented by Attorney The Law Offices of Bradley J. Bereznak
  • Patent number: 7875962
    Abstract: A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 25, 2011
    Assignee: Power Integrations, Inc.
    Inventors: Balu Balakrishnan, Brad L. Hawthorne, Stefan Bäurle
  • Patent number: 7871882
    Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
    Type: Grant
    Filed: December 20, 2008
    Date of Patent: January 18, 2011
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee
  • Patent number: 7872994
    Abstract: In one embodiment, a method includes steps of verifying, by a first server, that a user associated with an endpoint is authorized to access a service provided by a second server. The first server then sends a Session Initiation Protocol (SIP) out-of-dialog REFER with a Replaces header to the second server. A dialog identification ID of a session between the endpoint and the first server is embedded within the Replaces header. The SIP out-of-dialog REFER causes the second server to send a SIP INVITE with the Replaces header to the endpoint to establish a new session between the endpoint and the second server. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 18, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Juhee Garg, Randall B. Baird
  • Patent number: 7870590
    Abstract: A system for multicast streaming of programs over a packet network includes a node having a processor that conditions a video bitstream such that packets containing an I-frame are located near program specific information (PSI) packets, the processor marking a random join point (RJP) in the video bitstream immediately preceding the I-frame and PSI packets, the node outputting the conditioned and marked video bitstream across the packet network. An edge device of the network includes a buffer that caches packets of the conditioned and marked video bitstream video starting at the RJP, and sends the cached packets to a client receiver.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: January 11, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Ramanathan T. Jagadeesan, Kristen Marie Robins, Bich Tu Nguyen, Fang Wu
  • Patent number: 7863172
    Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: January 4, 2011
    Assignee: Power Integrations, Inc.
    Inventors: TingGang Zhu, Bryan S. Shelton, Marek K. Pabisz, Mark Gottfried, Linlin Liu, Milan Pophristic, Michael Murphy, Richard A. Stall
  • Patent number: 7864944
    Abstract: A system and method for handling a call from a caller to a call center includes an automatic call distributor (ACD) to receive the call and to route the call to an agent. A module operates to compute a rate of speech of the caller, and a display graphically displays the rate of speech of the caller to the agent during the call session. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: January 4, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Joseph F. Khouri, Mukul Jain, Labhesh Patel, Sanjeev Kumar, Gebran George Chahrouri
  • Patent number: 7859037
    Abstract: In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: December 28, 2010
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee, Martin H. Manley
  • Patent number: 7855950
    Abstract: A mechanism that provides congruent forwarding paths for unicast and multicast data traffic over a service provider core network includes issuing, by a receiver edge node, a request to join a multicast tree structure. A unicast path from the receiver edge node to a source node of the provider network is then established using a special message that contains an identifier. The identifier allows the unicast path through the core network to be aligned with the multicast tree structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: December 21, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: John M. Zwiebel, Ali Sajassi, Dino Farinacci, Daniel Alvarez
  • Patent number: 7849491
    Abstract: Apparatus for video gaming includes a box having a slot with an interface that connects to a game card providing a platform to run a software video game. The game card outputs video game data through the interface at a data rate of approximately 200 Mbps or greater. A unit processes the video game data for output to a display device. A wireless transceiver is included to receive the software video game via a wireless local area network (WLAN) and to transmit game information to a remote player having access to the WLAN during interactive play of the software video game. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: December 7, 2010
    Assignee: OnLive, Inc.
    Inventor: Stephen G. Perlman
  • Patent number: 7847815
    Abstract: In one embodiment, a method includes capturing a facial image of a participant to a video conference session from a video stream of the video conference session. A database containing a plurality a stored facial images is then accessed in an attempt to match the facial image with one of the stored facial images. Each stored facial image is associated with information in the database associated with a person, the information being retrieved in the event of a match. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: December 7, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Labhesh Patel, Sanjeev Kumar, Mukul Jain, Joseph F. Khouri
  • Patent number: 7843917
    Abstract: In one embodiment, a method includes sending upstream to a nearest neighbor node, by a Client Label Switched Router (LSR), a downstream label map message of a Server-Forwarding Equivalence Class type (S-FEC-DOWN). In response to the S-FEC-DOWN, a downstream forwarding state from the nearest neighbor node to the Client LSR is established. An upstream label map message of a Client-Forwarding Equivalence Class type (C-FEC UP) is received from the nearest neighbor node. An upstream forwarding state corresponding to the C-FEC UP is then established by the Client LSR.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: November 30, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Frank Brockners, Ali Sajassi, Robert James Goguen, Ijsbrand Wijnands
  • Patent number: 7844036
    Abstract: In one embodiment, a graphical user interface (“GUI”) enables the efficient composition and execution of a test of a message-based application, Web application, or SOA systems' capacity to receive, process and respond to message traffic. The GUI may be used to generate a test composition by dragging and dropping message clips onto one or more tracks. Each clip includes one or more message, with each track being organized into one or more bands. Each track and each band may run contemporaneously to send messages to a target device or application. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: November 30, 2010
    Assignee: SOASTA, Inc.
    Inventors: Kenneth C. Gardner, Craig R. Powers, Robert Charles Holcomb, Kendall J. Cosby, Tana Christine Jackson, Charles A. Vazac, Matthew Solnit, Michael Hemmert
  • Patent number: 7835370
    Abstract: A DSLAM aggregation topology VLAN bundling mechanism includes an edge device port that receives a packet from a Digital Subscriber Line Access Multiplexer (DSLAM) device, the packet including an inner Virtual Local Area Network (VLAN) tag that identifies a Digital Subscriber Line (DSL) subscriber. A processor of the edge device adds an outer VLAN tag to the packet, the outer VLAN tag identifying the DSLAM and a destination server coupled to an Ethernet access network. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: November 16, 2010
    Assignee: Cisco Technology, Inc.
    Inventor: Ali Sajassi
  • Patent number: 7829944
    Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: November 9, 2010
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 7816731
    Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: October 19, 2010
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Wayne Bryan Grabowski
  • Patent number: 7791132
    Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: September 7, 2010
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Donald Ray Disney
  • Patent number: 7793094
    Abstract: An intrusion detection system and method for a computer network includes a processor and one or more programs that run on the processor for application inspection of data packets traversing the computer network. The one or more programs also obtaining attribute information from the packets specific to a particular application and comparing the attribute information against a knowledge database that provides a baseline of normal network behavior. The processor raises an alarm whenever the attribute information exceeds a predetermined range of deviation from the baseline of normal network behavior.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: September 7, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Darshant B. Bhagat, Manjeri Krishnan, Karthikeyan M. Sadhasivam, Ravi K. Varanasi
  • Patent number: 7786533
    Abstract: A high-voltage transistor includes a drain, a source, and one or more drift regions extending from the drain toward the source. A field plate member laterally surrounds the drift regions and is insulated from the drift regions by a dielectric layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: August 31, 2010
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 7761110
    Abstract: A processor-implemented method of operation for managing a push-to-talk (PTT) session involving a plurality of participants includes applying a first floor control algorithm at a PTT server. The first floor control algorithm being selected from a plurality of algorithms that arbitrate among talk requests received from the participants. The method further includes changing, during the PTT session, from the first floor control algorithm to a second floor control algorithm at the PPT server. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: July 20, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Ashish Chotai, Sravan Vadlakonda, Binh Don Ha, Aseem Asthana, Shmuel Shaffer
  • Patent number: 7745291
    Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: June 29, 2010
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney