Abstract: A zero intermediate frequency radio device has an antenna for receiving a radio frequency signal, and a frequency down converter for down converting the received radio frequency signal to a zero intermediate frequency signal. The radio device further has controllable amplifier stages, controllable AC-coupling stages, controllable filter stages, and a received signal strength indicator. A signal resolving range of the received signal strength indicator is below a high dynamic range of the received radio frequency signal. The radio device further has an automatic gain controller. The automatic gain controller initially sets the gain of the Rx path of the radio device to a maximum of minimum gain, and then waits for DC-offsets in the Rx path to cancel. If, at maximum or minimum gain, a reading of the received signal strength indicator is within a particular range, the automatic gain controller sets the gain to the reading. Then, automatic gain control settles.

Abstract: A digital communication device having a dual conversion architecture. A first rf-mixing stage is provided followed by a second, quadrature, mixing stage of which output signals are sampled by means of an analog-to-digital converter and supplied to a digital signal processor (DSP) for further baseband processing. The A/D converter is a modified sigma delta analog-to-digital converter. A mixing function is added to the A/D-conversion function by modifying the input stage of a conventional sigma delta bitstream A/D converter. The result is a reduced number of IC-external components and a reduced power consumption.

Abstract: A fractional-N frequency synthesizer for use in a transmitter for transmitting TDMA signals, comprises a fourth order sigma-delta modulator(16) having an input for digitized signals, a FIR filter(18) having 2 taps coupled to an output of the sigma-delta modulator, the FIR filter (18) serving to increase the number of states on its output by one over the number of states on its input which is connected to an output of the sigma-delta modulator, and a phase locked loop(PLL) including a frequency divider(20) with an incremental ratio of 0.5 and having a control input coupled to an output of the FIR filter. The frequency divider (20) by having an incremental ratio of 0.5 enables the PLL to have a reference oscillator(24) operating at half the sampling frequency of the sigma-delta modulator(16).

Abstract: A variety of applications do not require a high data throughput. The standardization of the interface in the field of smart cards fixes the processing width at 1 bit. Therefore, it is effective to use a programmable structure which operates with a data width of one bit. A data processing arrangement in the form of a 1-chip implementation with a processing width of 1 bit can be used in chip cards for simple control and automation functions while utilizing serial protocols. This structure features uncomplicated circuitry, a small chip surface area, a wide field of application and a low power consumption.

Abstract: In order to unambiguously allocate a data carrier to an object, key information is written into the data carrier. Before writing-in the key information, secret identification information and open identification information is written into the data carrier. Copies of the secret and open information are stored in a central station. In the central station, for a particular data carrier, the open and secret information is associated with each other. In addition thereto, in the central station, object information for the particular object, and key information for the object are associated with each other. From the data carrier, the open identification information is sent to the central station to access the associated stored open and secret identification information so as to retrieve the stored secret identification information. In addition thereto, object information is sent to the central station to access the associated stored object and key information so as to retrieve the stored key information.