Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A gate-source structure and fabrication method for a static induction transistor. The method and the device are embodied by the epitaxial layer of, for example, high resistivity p-type semiconductor material grown on an epitaxial layer of high resistivity n-type semiconductor material. A silicon dioxide layer with source and gate windows is formed on the p-type epitaxial layer. Source grooves are formed in the p-type epitaxial layer at source window locations and the grooves are diffused with n-type impurities to form a diffusion region which extends to connect with the n-type epitaxial layer. Source and gate electrodes are formed in the source and gate windows.