Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier. The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract: An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Abstract: This invention relates to the color matching function used in connection with the luminance or white stretch function in a television video processor. Automatic adjustment in the amplitude of the color difference signals is provided to compensate for the effect of the stretch of the luminance signal in a provision called color matching. The general principal of color matching being, any percentage change in the amplitude of the luminance signal due to the white stretch effect, must be balanced by the same percentage changes in the color difference signal so that the ratio of the color signals can be maintained after matrixing. This accomplished by compensating the color difference signals by a varying amount that decreases with increasing the input luminance signal level when the level of the input luminance signal is above said selected threshold.

Abstract: A process creates contacts in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure. The cross-point structure includes memory cell matrices in which the bit lines are parallel unbroken diffusion strips extending along a column of the matrix with the contacts being provided through associated contact apertures defined through a dielectric layer deposited over a contact region defined on a semiconductor substrate at one end of the bit lines. The process calls for a step of implantation and following diffusion of contact areas provided in the substrate at opposite sides of each bit line to be contacted to widen the area designed to receive the contacts.

Abstract: A circuit and a method generate first and second triangular waveforms opposite in phase to each other. The circuit includes a capacitor having a first plate coupled to a first output at which the first triangular waveform is produced and a second plate coupled to a second output at which the second triangular waveform is produced. First and second switches are coupled between a first voltage reference and the first and second plates, respectively, of the capacitor. The circuit also includes a controller having a first output coupled to the control terminal of the first switch and a second output coupled to a controlled terminal of a second switch. The controller is structured to produce at the first and second outputs respective first and second control signals in opposition to each other and thereby control the first and second switches in opposition to each other.

Abstract: A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-decoding circuit has a push-pull output circuit with a pull-up transistor and a pull-down transistor and four parallel paths for the signal, a first path, supplied with low voltage, which drives the pull-up transistor during reading; a second path, supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path, supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path, supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages enable selectively one of the first and second path, and one of the third and fourth path, depending on the operative step.

Abstract: A band-gap regulator circuit produces a voltage reference having a temperature compensation for second order effects. The regulator circuit includes: a Brokaw cell for producing a first band-gap voltage reference Vbg; a circuit portion including a comparator connected to the Brokaw cell output for providing a compensation voltage value Vcorr; and a summing circuit that sums together the compensation voltage value Vcorr and the first band-gap voltage reference Vbg.

Abstract: An electronic regulator for driving a power device connected to an output load having a first portion and a second protection portion, the first portion including a controlled switching element connected upstream of the power device and controlled by a timer adapted to be operated in a short circuit or overload situation of the device, such that the load current can flow in the power device in a pulsed state clocked by the timer.

Abstract: A voltage regulator circuit produces a voltage reference with high line rejection even for low values of the supply voltage. The regulator is of the type that produces a regulated voltage value for a bandgap voltage generator and includes a regulation circuit portion and a reference circuit portion. The regulation circuit portions is supplied with the supply voltage and has an output at which the regulated voltage value is produced and an input that receives a voltage reference. The reference circuit portion produces the voltage reference and includes a first circuit leg that receives the supply voltage through a controlled switch and a second circuit leg that receives the regulated voltage value.

Abstract: A circuit device programs non-volatile memory cells having a single voltage supply, wherein each cell comprises a floating gate transistor having source and drain terminals and a control gate terminal, with the drain terminal being supplied a program voltage from a voltage booster circuit. The device includes a means of supplying a constant drain current to the drain terminal of the memory cell; an element for sampling the drain current drawn through the cell; and a means of voltage feedback driving the control gate terminal of the cell according to the sampled value of the drain current.

Abstract: A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.