Abstract: The present invention is directed to a method and apparatus for testing integrated circuits using a tester with a frequency limitation lower than what is needed to fully test the integrated circuit. Clock signals, each lower than that needed to test an integrated circuit at speed, are generated by a tester. These clock signals are connected to separate output pins of the integrated circuit. At least two of the input signals are out of phase with each other. The input clock signals are combined to create a test clock signal with a higher frequency, thus allowing the integrated circuit to be tested at its normal, operating frequency. A toggle signal may be provided to an additional pin on the integrated circuit. Use of the toggle signal allows test data to be written at the maximum frequency of the integrated circuit. The present invention does not create any significant delay during normal operation of the integrated circuit, and also does not create any significant layout penalty.