Patents Represented by Attorney, Agent or Law Firm Theordore E. Galanthay
  • Patent number: 6246704
    Abstract: An integrated circuit structure and method is capable of automatically tuning the duty cycle of a generated clock signal to any desired value. Tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a serial fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: June 12, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: Jason Siucheong So
  • Patent number: 6188998
    Abstract: In a method, according to the invention, of storing one or more natural membership functions of respectively one or more natural variables being each defined within a natural universe of discourse having a lowest natural value and a highest natural value, the natural membership functions are normalized through respective normalization coefficients so that they are defined within the same predetermined absolute universe of discourse having a lowest absolute value and a highest absolute value, thereby obtaining one or more absolute membership functions, respectively, and said absolute membership functions and said normalization coefficients are stored, taking account that identical absolute membership functions are stored only once.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: February 13, 2001
    Assignees: SGS-Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Antonino Cuce', Matteo Lo Presti
  • Patent number: 6169691
    Abstract: A method for restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The condition of the memory cell is determined, for example, when the memory is switched on, or based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: January 2, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Frank Lhermet, Pier Luigi Rolandi
  • Patent number: 6124751
    Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: September 26, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Albino Pidutti
  • Patent number: 6094073
    Abstract: The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: July 25, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Campardo, Rino Micheloni, Stefano Commodaro
  • Patent number: 6021121
    Abstract: A device for the selection of address words each having n bit locations and serving for addressing m different receiving locations of a digital communication module, in at least one of the receiving locations, including a digital acceptance module through which address words can be selected. The device has an address word segmenting module through which each address word received by the receiving location can be subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s. The device further has z digital segment filters whose inputs can each be fed with an address word segment, with each segment filter having the function of examining one address word segment each with respect to conformity with a predetermined segment bit pattern, and a filter output signal being available at the output of the respective segment filter, which in accordance with the examination result is either a conformity signal or a non-conformity signal.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: February 1, 2000
    Assignee: STMicroelectronics GmbH
    Inventor: Peter Heinrich