Patents Represented by Attorney Thomas DeMond
  • Patent number: 4996133
    Abstract: Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).
    Type: Grant
    Filed: December 23, 1987
    Date of Patent: February 26, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey E. Brighton, Douglas P. Verret