Abstract: A directionally sensitive, high contrast secondary electron detector having a novel geometrical configuration for use in scanning electron microscopes and other electron beam instruments. The aperture of the detector which is placed near the specimen is in non-parallel arrangement with the aperture which admits the primary beam. The geometry of the detector provides for tilting of the specimen with respect to the incident primary electron beam to improve sensitivity and signal-to-noise ratio in comparison with prior detectors. In the preferred embodiment, the shape of the upper grid of the detector is substantially that of a conic section, thereby preventing space-charge build-up during operation.

Abstract: A space-charge-limited (SCL) transistor is utilized as a photo-transistor. The preferred embodiments feature a base diffusion which is shallower than the standard SCL structure and a base geometry for increased light collection while maintaining the high current gain characteristic of SCL transistors.

Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BV.sub.ceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.

Abstract: Apparatus for incrementally advancing a sheet with high accuracy in which a single actuator causes both the incremental advance of a sheet-advancing roller and also the engagement of the sheet with a printing head upon completion of the incremental advance. The apparatus is particularly adapted to advance thermally sensitive paper past thermal print heads for line-at-a-time printing.

Abstract: A complementary field effect transistor structure which eliminates the problems caused by parasitic currents between devices. The currents are contained within parasitic bipolar devices formed between the various regions of the FETs. A portion of the collector current of the parasitic bipolar devices is drained away so that the loop gain is less than one. This is achieved by placing guard regions of conductivity type which are the same as the channel type of the transistors adjacent said regions. The guard region is preferably in the form of a continuous ring around its associated FET.

Abstract: A thermal display heater elements array for a comprising an array of semiconductor heater mesas having a larger cross-sectional area at the display surface than at the support surface. The preferred structure is in the shape of a truncated, inverted pyramid. The novel method includes forming the inverted heater elements by etching trenches in one surface of the semiconductor substrate and forming the heater mesas at the opposite surface, with the trenches defining the individual mesas.

Abstract: A space-charge-limited integrated circuit structure featuring optimized geometry to allow maximum packing density of the transistors in a semiconductor substrate.The widths of any two isolated regions of the same conductivity type are established in relation to the width of the region separating the isolated regions. The width of the region which separates two isolated regions having the same conductivity type as the high resistivity substrate must be greater than 0.75 times the width of either of the isolated regions. Conversely, the width of the region which separates the isolated regions having the opposite conductivity type to the substrate must be greater than 0.25 times the width of either of the isolated regions.