Abstract: A block data transfer system may comprise a microprocessor integrated within a bus controller, a bus, and a plurality of computer boards coupled together via the bus. A PAL (programmable array logic device), integrated within the bus controller, allows an efficient block transfer of data between components on the computer boards by asserting a binary signal to indicate to the bus controller when to continue the data transfer and when to truncate the data transfer. The PAL utilizes a counter, dependent upon the data transfer size, to control the binary indication signal. The binary signal overrides the architectural data transfer protocol, thereby eliminating "protocol overhead" timing associated in multiple data transfers by allowing the entire data block to transfer within one transfer protocol period.

Abstract: A method of driving a motor without initial back rotation includes the steps of identifying a rest position 22 of a storage medium 20, mapping the rest position of storage medium 20 to a motor drive sequence, and driving the motor with the motor drive sequence, thereby enabling motor start-up without back rotation. The method is applicable to unipolar and bipolar drive methods as well as inductive read type and magneto-resistive type heads.

Abstract: A method of improving efficiency in computer systems through a novel arbitration scheme is disclosed. The arbitration scheme includes a bus arbiter circuit that transparently operates in both central arbitration and distributed arbitration computer systems. The bus arbiter circuit includes an arbitration request sequencer, an arbitration competition protocol sequencer, a multiplexer, a latch, two comparators, and a series of control status registers that together provide increased system efficiency by effectively self-preempting competition priorities on its own board, thus allowing tasks with the highest priorities to compete for mastership of the bus and eliminating priority inversions.

Abstract: A phase locked loop circuit 11 includes a phase detection circuit 12, a means for phase adjustment, and a recovery circuit 18. The phase detection circuit 12 monitors the phase relationship between two signals and communicates the phase relationship to the phase adjustment means. The phase adjustment means provides appropriate delay to one of the signals to synchronize the two signals. The recover circuit 18 monitors the phase adjustment means for synchronization failures and provides appropriate notice to the phase adjustment means. The phase locked loop circuit 11 provides improved phase jitter resolution through the phase adjustment means. The circuit provides failure identification and correction through the recovery circuit resulting in improved phase locked loop circuit performance and reliability.

Abstract: A low power, break before make output circuit includes an output transistor pair 12 and 14, a first control circuit 20, a second control circuit 22, a first comparator 16, and a second comparator 18. First control circuit 20 has a first input coupled to a first digital control input and an output coupled to a control terminal of a first transistor 12 in the output transistor pair. Second control circuit 22 has a first input coupled to a second digital control input and an output coupled to a control terminal of a second transistor 14 in the output transistor pair. First comparator 16 has an input connected to the output of first control circuit 20 and an output connected to the second input of second control circuit 22. First comparator 16 compares a voltage at the control terminal of first transistor 12 to a first predetermined voltage and formulates a voltage at its output in response to the comparison.

Abstract: A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed on the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

Abstract: A terminated driver circuit 10 having a controlled output impedance includes an external impedance 12 connected to a bias generator circuit 20 which is operable to generate a plurality of bias voltages in response to a reference current generated by bias generator circuit 20 wherein the reference current magnitude is a function of external impedance 12. An output driver circuit 30 is connected to bias generator circuit 20. Output driver circuit 30 has a plurality of output devices connected to a transmission line and is operable to receive the plurality of bias voltages from bias generator circuit 20 and multiplex them such that only a single bias voltage is driving a single output device at a time. The plurality of bias voltages causes the plurality of output devices to have specific, controlled impedances when conducting wherein the controlled output impedances match the characteristic impedance of a transmission line 40 being driven by terminated driver circuit 10 thereby reducing waveform reflections.

Abstract: An output circuit includes a power MOSFET with a gate connected to a plurality of diodes, the plurality of diodes forming a diode string. A resistor is connected in parallel with the diode string. A switch is connected between the opposite end of the diode string and circuit ground. A control terminal of the switch is connected to the circuit input and determines whether the circuit is turned on or turned off. An inductive load is connected to a drain terminal of the power MOSFET. The opposite end of the inductive load is connected to a power supply. A source terminal of the power MOSFET is connected to circuit ground thus providing a low-side driver circuit configuration. The resistor and diode string, connected in parallel, along with the switch provide a two-phase, soft turn-off mechanism which allows the power MOSFET to dissipate the energy stored in the inductive load without the power MOSFET entering breakdown, therefore improving the circuit's reliability.

Abstract: A torque hinge 20 includes a shaft 14 surrounded with a coating 22 fixed to the shaft 14. The coated shaft 18 fits within a housing cavity 26 such that the coated shaft 18 is in frictional contact with the housing cavity 26. The frictional contact provides sufficient torque to torque hinge 20 to provide constant resistance through the torque hinge's entire range of motion.

Abstract: An electrostatic discharge protection circuit 11 coupled between an input pad 12 and operational circuitry 20 includes a primary clamp circuit 14 coupled to input pad 12, and a current limit circuit 16 coupled to primary clamp circuit 14. Primary clamp circuit 14 clamps an electrostatic discharge voltage to a first voltage value. Operational circuitry 20, susceptible to damage due to an electrostatic discharge, is coupled to current limit circuit 16 and a zener diode 30 is coupled between current limit circuit 16 and a ground potential. Zener diode 30 has a cathode terminal coupled to current limit circuit 16 and an anode terminal coupled to ground potential. Zener diode 30 further clamps a voltage across operational circuitry 20 to a second voltage which is less than 10 V, thereby protecting operational circuitry 20 from damage due to electrostatic discharge.

Abstract: A system and method for communicating between an identification reader 12 and a transponder unit 10 is disclosed herein. A first interrogation signal is transmitted from the reader 12. This first interrogation signal having a first read range. A first response signal is then received at the reader 12 after which a second interrogation signal is transmitted from the reader 12. The second interrogation signal has a second read range which is different than said first read range. The read range can be varied by varying either the amplitude or duration of the power level of the interrogation signal. A second response signal is then received at the reader 12. These consecutive responses are then compared determine a correct response signal which can be displayed.

Abstract: A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and "live-lock" conditions.

Abstract: An optical tracking and positioning system is provided which comprises a beam source 14 which generates a beam which is transmitted through a splitter/filter 16. The beam issues from splitter/filter 16 and is selectively deflected to areas of an optical storage medium 12 by a mirror 18 which is controlled by a mirror control system 20. The beam is transmitted from mirror 18 through correction optics 22 and reflects off the surface of the optical storage medium 12. The beam returns along a coincident path and is separated by splitter/filter 16 and directed to a detector 24 which reads the data stored in optical storage medium 12. According to a preferred embodiment of the present invention, the mirror 18 comprises a deformable mirror device 26.

Abstract: An autoranging digital/analog (D/A) phase locked loop (PLL) 10 includes a frequency discriminator circuit 12 connected to a shift register 14. Shift register 14 is connected to a voltage controlled oscillator circuit (VCO) 16. VCO 16 is connected to generic counter 17. Counter 17 is optional in this preferred embodiment. Counter 17 is connected to a phase detector 13 and frequency discriminator 12. Phase detector 13 is connected to a charge pump control circuit 15. Charge pump control circuit 15 is also connected to VCO 16. A second generic counter 11 is connected to frequency discriminator 12. Second counter 11 is also optional in this preferred embodiment. First generic counter 17 and second generic counter 11 can be implemented to reduce the phase detector frequency relative to VCO 16 or a reference clock signal frequency. Ratios of M to N allow frequency multiplication or division of VCO 16 relative to the reference clock signal frequency.

Abstract: A communication system (20) is provided with multiple purpose personal communication devices (50 and 150). Each communication device (50 and 150) includes a touch-sensitive visual display (60 and 160) to communicate text and graphic information to and from the user and for operating the communication device (50 and 150). Voice activation (78) and voice control capabilities (76) are included within communication devices (50 and 150) to perform the same functions as the touch-sensitive visual display (60 and 160). The communication device includes a built-in modem (82), audio input and output (52 and 53), telephone jacks (86), and wireless communication (90). A plurality of application modules (100) are used with personal communication devices (50 and 150) to perform a wide variety of communication functions such as information retrievable, on-line data base services, electronic and voice mail.

Abstract: An improved data sampling system for sampling data transmission in a computer system includes a reference clock, a delay locked loop circuit, a packet enable circuit, a delayed selector control circuit, a sample selector, and a sample circuit. The devices may be constructed on a single semiconductor substrate and may be connected to a bus structure having a microcomputer and a plurality of boards coupled to it. The delay locked loop circuit generates accurate delayed clock signals based on the reference clock. A positive edge synchronizer circuit, within the delay locked loop, serves as a programmable phase adjust for the sampling system. The positive edge synchronizer ensures proper phase relationship between the chosen delayed clock signal and the incoming data across semiconductor process variations. Packet enable circuit informs the delayed control circuit and the sample circuit when a start bit or stop bit is initiated in a data packet and enables those circuit blocks accordingly.

Abstract: A digital signal processor (32) having an associated memory (34) executes a program interpreter (40) which interprets program routines stored in a program storage area (42) of the memory (34). The program routines are portions of a larger application program. The program routines are downloaded via control of a CPU (20) which stores a library of program routines in its associated program memory (28).

Abstract: An integrated voice communication system is provided which includes first circuitry for delivering a stored message to a subscriber calling party upon the receipt of a first command. Second circuitry is coupled to the first circuitry and is operable to create a direct connection with a selected called party without exiting the system upon the receipt of a second command.

Abstract: A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.