Abstract: An equalization method receiving a received sample to generate an equalizer output. A channel profile is first provided, comprising a main path and a plurality of echoes distributed in time domain. Echoes anterior to the main path are precursors, and echoes posterior to the main path are postcursors. The received sample is filtered with a linear equalizer (LE) comprising a plurality of taps to generate an LE output. A slicer slices the equalizer output to generate a sliced sample. The sliced sample is further sent to a decision feedback equalizer (DFE) comprising a plurality of taps to generate a DFE output. Simultaneously, an equalizer span is determined based on the channel profile. The LE output and the DFE output are combined to generate the equalizer output having the equalizer span. The equalizer span is determined by allocating the position of main tap.

Abstract: A data management method for a network. Whether a first record in a database is updated is automatically determined. Content of the first record is organized in a hierarchical structure. Which of a group of clients is affected by update of the first record is automatically determined. A data format corresponding to an affected client is automatically determined. A message is automatically generated by modifying the hierarchical structure according to the data format. The message comprising the result of modifying the hierarchical structure is automatically transmitted to the affected client.

Abstract: A method of manufacturing a coil inductor and a coil inductor are provided. A plurality of conductive bottom structures are formed to be lying on a first dielectric layer. A plurality pairs of conductive side structures are then formed, wherein each pair of the conductive side structure stand on top surface of a first end and a second end of each conductive bottom structure respectively; a second dielectric layer is formed on the first dielectric layer, coating the bottom and side structures; and a plurality of conductive top structures are formed to be lying on the second dielectric layer, wherein each conductive top structure electrically connects each pair of the conductive side structures, wherein the conductive bottom structures, the conductive side structures and the conductive top structures together form a conductive coil structure.

Abstract: A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.

Abstract: An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.

Abstract: A swiveling display device, capable of easy assembly and disassembly, includes a main body, a supporting arm joined to the main body, and a base having a positioning hole. The supporting arm is inserted into and detachably engages the positioning hole in such a manner that the supporting arm can rotate within a predetermined range.

Abstract: A graphics processing unit (“GPU”) is configured to receive an interrupt command from a CPU or internal interrupt event while the GPU is processing a first context. The GPU saves the first context to memory and records a precise processing position for the first context corresponding to the point interrupted. Thereafter, the GPU loads a second context to the processing portion of the GPU from memory and begins executing instructions associated with the second context. After the second context is complete of if an interrupt command directs restoration of the first context, the GPU's processor switches to the first context for continued processing. The first context is retrieved from memory and restored to the precise processing position where previously interrupted. The GPU then processes a remainder portion of the first context from the precise processing point to an end of the first context.

Abstract: Methods of noise reduction and edge enhancement in image processing. An exemplary method comprises extracting a plurality of pixels from the video signal, evaluating measures of edge existence in a plurality of directions within the extracted pixels, determining a level of variation from the measures of edge existence, mapping the level of variation to a first and second control signal in accordance with a predetermined function, performing noise reduction on the extracted pixels according to the first control signal, and performing edge enhancement on the extracted pixels according to the second control signal.

Abstract: A system for production planning. A MES provides production information corresponding to a preset time period of a production line, monitors processing of work-in-process (WIP), and provides processing status information of the WIP. A processor determines a move target for the WIP in the production line during the preset time period according to the production information, calculates achieved moves of the WIP, and compares the move target and the achieved moves.

Abstract: A pixel electrode structure for a liquid crystal display with a high aperture ratio increases the aperture ratio and eliminates Mura phenomenon. Any two adjacent pixel electrodes are disconnected to each other. Each pixel electrode comprises a first-lengthwise periphery that overlaps a first-adjacent data line to form a first overlapping portion, and a second-lengthwise periphery that overlaps a second-adjacent data line to form a second overlapping portion. The first-lengthwise periphery and the second-lengthwise periphery have an identical triangle-wave profile and are symmetrical to each other. The triangle-wave profile is formed by connecting a plurality of right-angled and equilateral triangles.

Abstract: A voltage level shifter. The voltage level shifter comprises a shifter unit and a controller. The shifter unit outputs a third signal according to a first signal and a second signal. When the first signal remains at a first level a current path is formed in the shifter unit. The controller is coupled to the shifter unit and stops the current path when the first signal remains at the first level.

Abstract: A plasma display panel. Front and rear plates are spaced by a rib structure that is disposed on the rear plate with Neon gas filled therebetween. The rib structure partitions off the rear plate into a plurality of first, second and third sub-pixels adjacent to each other, wherein both of the first and second sub-pixels are smaller than the third one. Red, green and blue phosphors are disposed in the first, second and third sub-pixels respectively, wherein adjacent first, second and third sub-pixels form a pixel.

Abstract: An electronic device. The electronic device comprising a host, and a module structure is disposed in the host for calculating data. The module structure has a first substrate, a process unit, a heat-dissipating device and a second substrate. The first substrate is a motherboard of the electronic device, and the process unit is disposed on the first substrate, and the heat-dissipating device is attached to the process unit and disposed on the first substrate. The first substrate and the second substrate have the same structure and texture. The first substrate and the second substrate are blanketed from a multi-layer structure or sheet used for the motherboard.

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract: A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

Abstract: A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the-overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.