Patents Represented by Attorney, Agent or Law Firm Thomas, Kayden, Worstemeyer & Risley
  • Patent number: 7078349
    Abstract: A self-aligned conductive region to active region structure is disclosed in which parallel active regions of a semiconductor region of a substrate, which extends to a surface, are separated by STI regions. The STI regions have an insulator liner layer grown over their sides and are filled with an insulator filler layer. Equally spaced gate insulator regions, formed prior to the STI regions, are disposed over the active regions and overlap a portion of the insulator liner layer. Conductive regions, formed prior to the STI regions, are disposed over the gate insulator regions.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chia-Ta Hsieh
  • Patent number: 6245627
    Abstract: A method of fabricating a load resistor for an SRAM. A substrate has a polysilicon layer formed thereon through a buried contact process. An inter-layer dielectric layer is formed over the substrate and then patterned to form an opening that exposes the polysilicon layer. A poly via is then formed in the opening to serve as a load resistor. The inter-layer dielectric layer is patterned to form a contact window, which is then filled with a conductive layer to form a contact.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: June 12, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Ji Chen, Shih-Ying Hsu