Abstract: A nonvolatile memory array includes a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping the first plurality of traces at a plurality of intersection regions, and a plurality of memory cells formed on the substrate. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of trace and includes a bidirectionally conducting nonlinear resistance selection device and a magneto-resistive element electrically coupled in series with the selection device. The array is biased during a read operation by biasing a selected trace of a first plurality of electrically conductive traces at a first bias potential. All other traces of the first plurality of conductive traces are biased at a second bias potential. A selected trace of a second plurality of conductive traces is biased at a third bias potential.

Abstract: A nonvolatile memory cell includes a substrate, a diode, a first conductive line, a magnetic tunnel junction device, a by-pass conductor and a second conductive line. The diode is formed in the substrate and includes an n-type region and a p-type region. The first conductive line is formed on the substrate and is electrically connected to the n-type region of the diode. The magnetic tunnel junction device is formed on the first conductive line. The by-pass conductor electrically connects the p-type region of the diode to the magnetic tunnel junction device. The second conductive line is formed on and is electrically connected to the magnetic tunnel junction device.

Abstract: A nonvolatile memory array includes a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping the first plurality of traces at a plurality of intersection regions, and a plurality of memory cells formed on the substrate. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces and includes a bidirectionally conducting nonlinear resistance selection device and a magneto-resistive element electrically coupled in series with the selection device. The array is biased during a read operation by biasing a selected trace of a first plurality of electrically conductive traces at a first bias potential. All other traces of the first plurality of conductive traces are biased at a second bias potential. A selected trace of a second plurality of conductive traces is biased at a third bias potential.