Abstract: A composition and method for the treatment of chronic sinusitis in which a composition containing desirable colonial bacteria is applied externally in the form of either a spray or a flush. The bacteria are selected from the genus Lactobacillus and the genus Bifidobacterium. The selected bacteria are provided in a therapeutically effective amount in a water solution.

Abstract: The trench-isolation structures for fabricating semiconductor devices using two different multilayer masking structures are disclosed by the present invention, in which the extended buffer spacers located in the isolation regions are formed on the sidewalls of two different multilayer masking structures having a masking dielectric layer on a pad-oxide layer and a masking dielectric layer on a conductive layer over a gate-oxide layer. The extended buffer spacers not only act as the etching mask for forming the trenches in the semiconductor substrate but also play significant roles for obtaining high-reliability and high-efficiency trench isolation of the present invention. The first role of the extended buffer spacers of the present invention is to offer the buffer regions for preventing the bird's beak formation around the edge of the active region during the thermal oxidation of the trench surface, so that the active area used to fabricate the active device is not sacrificed.

Abstract: The focus controlling system of the present invention can include a calibration paper, an image capturing device, an input interface, and a processing and controlling device. The image capturing device is employed for scanning the calibration paper. The image capturing device has a focus point adjusting mechanism. The input interface is utilized for receiving a location data of a scanning point. The processing and controlling device is responsive to the input interface and the image capturing device to control the focus point adjusting mechanism. The focus controlling method of the present invention includes the following steps. First, a scanning point is set or detected and a compensated magnification ratio for the scanning point is then calculated. A focus point of a image capturing device is adjusted and a calibration paper is scanned. The adjusting step and the scanning step are then repeated until a magnification ratio of the calibration paper is about the value of the compensated magnification ratio.

Abstract: The present invention proposes a die seal ring. The provided die seal ring is formed on a substrate and is used to encompass a die by locating between the die and adjacent scribe lines. Moreover, the provided die seal ring comprises a plurality of dielectric layers and a plurality of metal structures, wherein any metal structure is not overlapped with other metal structures. Moreover, dielectric layers are located on the substrate in sequence, and each metal structure is stacked by one metal ring and one metal plug. In addition, any metal ring is located on a dielectric layer and is covered by another dielectric layer, and metal rings of different metal structures are located on different dielectric layers. Further, any metal plug is located in the dielectric layers and is used to connect the metal ring to the substrate. Of course, if the aspect ratio of any metal plug is too large to be properly formed, an appendant metal ring is used to reduce the aspect ration of the metal plug.

Abstract: A method for upgrading qualities of DRAM capacitors and wafer-to-wafer uniformity is disclosed. In order to effectively prevent wafers from contaminations, the invention uses an additional silane purge process in situ before performing a SHSG seeding process on the wafers. The silane purge process of this invention utilizes the original silane seeding gas inlet. In this manner, not only thicknesses and surface areas of the SHSG seeds and capacitances of DRAMs can be increased, but also wafer-to-wafer uniformity can be upgraded.

Abstract: A rotary piston internal combustion engine comprises a substantially circular-cylindrical compression space (3) and a substantially circular-cylindrical working space (4), rotary pistons (7, 8) which can rotate together about an axis of the compression space (3) and the working space (4), being disposed in the compression space (3) and the working space (4) are slides (19) which are arranged so as to be movable in the radial direction in order to abut sealingly the surface of the respective rotary piston (7, 8). The periphery of the working space has a first exhaust aperture (26). The working space has further exhaust apertures (27) which can be closed by exhaust valves (15) which can be closed and opened successively by means of an adjusting arrangement (17).

Abstract: A method for fabricating a non-volatile memory on the semiconductor substrate is disclosed. First of all, a plurality of trench isolation regions are formed. Then, firstly implanting ions of a first conductivity type and second conductivity type are carried out. Secondly implanting ions of the first conductivity type and second conductivity type are carried out. Then, a first oxide layer is deposited and the first oxide layer is removed. A second oxide layer is deposited. A portion of second oxide is removed, thus, a portion of second oxide layer is remained. A third oxide layer is formed. A first polysilicon layer is formed. The first polysilicon layer is etched. A oxide-nitride-oxide layer is formed. Consequentially, the oxide-nitride-oxide layer are all etched. The second polysilicon on is formed. A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched. Thus, capacitor columns are formed.

Abstract: A new method for forming integrated circuits is disclosed. The method includes the following procedures. A substrate over which a high integration region and a low integration region beside the high integration region are formed. Then dummy layer is formed on the low integration region. Next, a dielectric layer is formed on the high integration region and the dummy layer on the low integration region. Finally, the dielectric layer is planarized.

Abstract: A sleeve means is described. The sleeve means comprises a round plane and ring-shaped side adjacent to the round plane. The round plane has a central hole and six periphery holes thereon. The central hole and six peripheral holes respectively correspond to a central opening and six screw holes of a heater adapter flange used in Gasonics L3510 (trademark) etcher. The sleeve means could be jacketed onto the heater adapter flange for dispersing the stress on and reducing deformation of the heater adapter flange when the heater adapter flange is mounted on the chamber of the etcher.

Abstract: A structure of manufacture of a semiconductor die on a lead-on-chip (LOC) packaging using a flexible copper plated tape and a standard lead frame is disclosed. A semiconductor die with bonding pads in the center is interconnected to a flexible copper plated tape by copper trace, solder bumps, or gold bump. The flexible copper plated tape is then placed on top of and attached to a standard lead frame. The configuration of a flexible copper plated tape, such material includes polymide tape, matches the configuration of a lead frame that allows the use of a standard outer lead frame. The configuration of a polymide tape provides greater flexibility in the placement of bonding pads anywhere on a semiconductor die without limiting the bonding pads to be placed in the center of a semiconductor die.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of LPD oxide trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. Finally, the standard processes can be employed for fabricating the CMOS transistors on the substrate.