Abstract: A protection device which protects against charge build up on a thin oxide gate during plasma etching is provided. The protection device may be described as a floating well PMOS device. When the PMOS transistor is formed, a lateral parasitic pnp transistor is also formed. In the lateral pnp device the base is floating, the collector is connected to ground and the emitter is connected to the gates of the host PMOS protection device and the device to be protected. In operation, the gate of the PMOS transistor is tied to the source of the PMOS transistor so that the PMOS transistor is off. Thus, the lateral pnp transistor controls the charging and discharging of the charge stored on the gate oxide. Excessive charge build up is prevented by the breakdown voltage of the lateral pnp transistor. Because protection is achieved by pnp breakdown operation, the size of the pnp protection device can be substantially lower than other protection devices.

Abstract: The flip chip package described is comprised of a substrate, a ring structure attached to the substrate, a heat removal structure, and a chip thermally coupled to the heat removal structure. The package lid is comprised of a ring structure and a heat removal structure. The ring structure and heat removal structure are separated until after attachment of the ring structure to the substrate allowing the ring structure to be brazed to the substrate. Brazing the ring structure to the substrate decreases the mechanical stress to the chip. A die attach material, between the first major surface of the die and the first major surface of the heat removal structure, adheres the die to and thermally couples the die to the heat removal structure. The die attach layer is of a predetermined thickness and thus provides a determined low thermal resistance making the thermal performance of the package certain.