Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

Abstract: A multilayer circuit board is provided that includes at least two insulating layers each sandwiched by circuit layers, thus having at least one internal circuit layer sandwiched by the at least two insulating layers. Via holes are formed in one or more of the insulating layers at the same pitch as bump electrodes of an integrated circuit chip, which permit insertion of the bump electrodes of an integrated circuit chip into the via holes of the multilayer circuit board. Metal films formed within the via holes are electrically connected to at least one of the circuit layers. An internal capacitor may be formed in a predetermined area of an insulating layer and predetermined areas of circuit layers which sandwich the predetermined area of the insulating layer and are opposed to each other. An internal resistor may be formed in an inner circuit layer.

Abstract: A method and system for performing the method are provided for designing a mask layout that includes selecting simulation sites for optical proximity correction (OPC) or mask verification, prior to fragmentation of shape edges. The primary simulation sites are selected based upon the influence of adjacent shapes, and then fragmentation is performed based on the primary simulation sites. Preferably, the simulation sites are selected by initial simulation within a region of influence of the vertices of mask shapes. The extrema of the resulting simulations are identified, and the intersection of a projection from the extrema to shape edges is used to define the primary simulation sites. Fragmentation of the edges may then be performed as long as the primary simulation sites thus selected are retained. The resulting simulation sites will allow the OPC engine to more effectively correct the shapes where the greatest influences will occur.

Abstract: A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.

Abstract: A method is provided for forming a film stack in which a first film including a first polymer is formed on a substrate. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface disposed on the first film. The second film can have a thickness at which a free energy of the second film would be negative if the second film were disposed directly on the substrate. Desirably, the resulting second film is substantially free of dewetting defects.

Abstract: A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a common orientation. The soft foil is positioned on a clam-receiving tool and a vacuumed caved cover clam is fitted on the balls and then pushed to cut and separate the polymer sheet from the copper ball surface. The vacuumed caved cover clam is then lifted with the oriented copper balls entrapped inside and the vacuumed caved cover clam places the entrapped balls on the laminate pads, with a deposit of low melt alloy. The air vacuum is deactivated and the cover is lifted, leaving the balls positioned on the pads while the soldering process is initiated and solder joints are formed to fix the balls.

Abstract: A fast method of verifying a lithographic mask design is provided wherein catastrophic errors are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models, including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding resist models are constructed that may include only SOCS kernel terms corresponding to the optical model, or may include image trait terms of varying influence ranges. Errors associated with excessive light, such as bridging, side-lobe or SRAF printing errors, are preferably identified with bright field simulations, while errors associated with insufficient light, such as necking or line-end shortening overlay errors, are preferably identified with dark field simulations.

Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

Abstract: A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

Abstract: A system, method and recording medium are provided for generating patterns of a paired set of a block mask and a phase shift mask from a data set defining a circuit layout to be provided on a substrate. A circuit layout is inputted and critical segments of the circuit layout are identified. Then, based on the identified critical segments, block mask patterns are generated and legalized for inclusion in a block mask. Thereafter, based on the identified critical segments and the block mask patterns, phase mask patterns are generated, legalized and colored to define a phase shift mask for use in a dual exposure method with the block mask for patterning the identified critical segments of the circuit layout.

Abstract: A film stack is provided in which a first film including a first polymer directly contacts a surface of a substrate at which a given material is exposed. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface contacting the first film. The second film can have a thickness at which a free energy of the second film would be negative if the second film were disposed directly on the substrate. Desirably, the resulting second film is substantially free of dewetting defects.

Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: An optical-fiber based light channel system is included in an ion/electron beam tool for imaging and/or processing integrated circuits. The optical channel system includes an image collection portion, an optical fiber image transmission portion and a detector portion. The image collection portion includes micro-optical components and has submillimeter dimensions, so that it is easily accommodated within the working distance of the ion/electron beam tool. The entire system is sufficiently compact and lightweight so that it may easily be mounted on a translation stage inside the sample chamber, which permits the optical channel to be mechanically extended and retracted to avoid blocking the primary ion or electron beam. The system may be mounted to a translation stage or to a gas injector assembly, which may itself be mounted to a flange plate on the chamber wall with feed-through ports for electrical and optical signals.

Abstract: A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a simulation target that is used as the new target within the MBOPC process. The pattern dependent portion of the model is used as the process model in the MBOPC algorithm. This results final mask designs that result in improved across-chip line width variations, and a more robust MBOPC process.

Abstract: A method, program product and system is disclosed for performing optical proximity correction (OPC) wherein mask shapes are fragmented based on the effective image processing influence of neighboring shapes on the shape to be fragmented. Neighboring shapes are smoothed prior to determining their influence on the fragmentation of the shape of interest, where the amount of smoothing of a neighboring shape increases as the influence of the neighboring shape on the image process of the shape of interest decreases. A preferred embodiment includes the use of multiple regions of interactions (ROIs) around the shape of interest, and assigning a smoothing parameter to a given ROI that increases as the influence of shapes in that ROI decreases with respect to the shape to be fragmented. The invention provides for accurate OPC that is also efficient.

Abstract: The invention relates to a system and method of detecting impurities in a cylindrically shaped transparent medium, wherein the cylindrically shaped transparent medium is illuminated with electromagnetic radiation, and the radiation having components emerging radially from the medium, and at least some of the components are received by a detector for detecting impurities of the medium. The components are detected at a multiplicity of relative angular positions around the symmetry axis of the cylinder, so as to form an impurity diagram that may be analyzed to detect and measure impurities in the medium.

Abstract: A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not the destination address of an access by the processor to ROM and SRAM is within a predetermined protected area, and internal registers and multiplexers as access control means. If a control instruction for the processor has been detected and an execution of an access from the processor to the protected area has been detected, the destination address of the access is replaced with addresses of a ROM and SRAM of an additional circuitry block that have been prepared by developers.