Abstract: A method, apparatus and program product for automatically detecting the configuration of a hardware platform, generating the communications necessary to request the correct OS for the platform, authenticating the request at a remote server, detecting the image class based on a class node policy, and downloading the correct OS to the requesting platform while avoiding any necessity of inventorying or entering node-specific information such as a MAC (Media Access Control) address or UUID (Universally Unique Identifier).

Abstract: Sessions states within virtual machine (VM) environments are maintained. Each VM environment hosts a guest operating system (OS) and one or more application programs running. The guest OS and the application computer programs of each VM environment constitute a session. A connection broker maintains a state machine as to states of the sessions and permits transitions among the states in response to messages, commands, and internal decisions. Different types of agents may send the messages, and the commands. The states of the sessions may include a pending state and a number of other states. The pending state is an interim state that indicates a session is being transitioned from one of the other states to another of the other states. These other states may include an offline state, an online-down state, an online-up state, a suspended state, an active state, an idle state, a disconnected state, and a failed state.

Abstract: A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

Abstract: A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected.

Abstract: A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals.

Abstract: A method and circuit for summing multiples vectors is disclosed. The method includes receiving a set of input vectors and generating a set of decoded summation vectors. Each of the set of decoded summation vectors indicates the value of at least a portion of the vector sum. The method further includes generating a set of decoded carry vectors. Each carry vector is used to select the summation vector for an adjacent portion of the vector sum from a set of preliminary summation vectors. In one embodiment, the method further includes counting the number of high bits in each bit position of the input vectors and generating decoded high bit count vectors based upon the counting to facilitate the generation of decoded summation vectors. In one embodiment, the set of preliminary vectors includes an initial preliminary summation vector and a set of adjacent summation vectors. In this embodiment each adjacent summation vector is achieved with a 1-bit rotation of the preceding adjacent summation vector.

Abstract: A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch.

Abstract: A method for verifying an integrated circuit design includes generating verification coverage information by simulating the operation of the integrated circuit. The verification coverage information is then analyzed to determine a set of missing coverage states. A set of verification directives based on the set of missing coverage states is composed and a set of test cases is generated, based on the verification directives, to simulate the missing coverage states. Analyzing the verification coverage information may include decomposing the verification coverage information into a set of basic coverage tasks (BCTs), wherein each BCT is a generic representation of a corresponding task. Decomposing the verification coverage information into a set of BCTs may comprise decomposing the verification coverage information into a set of covered BCTs and a set of BCT holes, wherein the covered BCTs represent verification states covered by the simulation and BCT holes represent verification states not covered.