Abstract: Described is a system for diagnosis and prognosis of a component. The system is configured to receive a signal from a component. The signal is representative of a current health observation of the component. The system also computes a present likelihood of the component failure based on the signal. Additionally, the system computes a future likelihood of failure of the component for a given future mission. Through diagnosis, a user can determine the present health of the component, and based on the present health and future mission, determine whether or not the component will fail in the future mission.

Abstract: A broadcast routing protocol and system for the efficient dissemination of control information in ad-hoc networks is disclosed. First, cost is assigned for each link and/or node in the network. In some aspects, cost is assigned using minimum inverse degree (MID-) or combined (C-) cost. Next, a graph-theoretic entity is computed at each node. In some aspects, this entity is Minimum Spanning Tree (MST) or Modified Minimum Weighted Node Cover. Finally, an appropriate packet forwarding protocol is used to forward control information. The present invention exhibits improved bandwidth consumption versus flooding and is robust in several node mobility scenarios.

Abstract: Described is a method for conforming electronics to arbitrary shapes. The method comprises acts of forming a device structure to have a growth substrate, an etch stop layer affixed with the growth substrate, and a micro-electronic array. The micro-electronic array comprises a plurality of components atop the etch stop layer. The micro-electronic array is thereafter embedded into a shrinkable layer. The shrinkable layer is then mounted onto a handle wafer that includes a layer of adhering film with the shrinkable layer being pressed into the layer of adhering film. The growth substrate and the etch stop layer are thereafter removed. The adhering film is then dissolved to demount the micro-electronic array and shrinkable layer. Finally, the shrinkable layer is shrunk to conform the micro-electronic array to a three-dimensional shape, with the growth orientation flipped such that metal interconnects may be made to both the top and bottom of the chip.