Abstract: In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.

Abstract: In PCI-Express and alike communications systems, number of lanes used per channel or port can vary as a result of negotiated lane aggregation during network bring-up. Disclosed are systems and methods for efficiently realigning packet data and stripping out control bytes in a by-eight port configuration as the packet data ingresses from the physical layer (PL), past the data link layer (DL) and into the transaction layer (TL). It is shown that data routing can be reduced to just two, mux-selectable permutations based on whether the STP (start of packet) character arrives in an even numbered double-word side (DW0) or an odd-numbered double-word side (DW1) of a physical layer register.

Abstract: Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or extended over multiple clock periods. Automated clock relationship detection between two clocks may comprise (a) a shift register synchronizer that reduces the possibility of metastability while capturing and temporarily storing samples of the first clock in response to cycles of the second clock and (b) an evaluator that processes the samples to determine the relationship. A clock relationship detector may also determine the relationship of two clocks by arbitrating a plurality of preliminary determinations of the relationship. Delays may be applied so that each of several detectors receives a clock at a different time, which may avoid metastability in the majority of detectors. The relationship may be used to reliably determine an operating mode of logic driven by one of the clocks.

Abstract: Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.

Abstract: An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) replay data; and (3) to-be egressed data. Additionally, a shared free space (4) is managed between the storage areas of the (2) replay data and (3) the to-be egressed data. The to-be egressed data (PdBx) is allowed to enter into (to be written into) a front-end raceway portion of the integrated memory structure at a rate which can be substantially greater than that allowed for corresponding egressing packet data (PdUx). Thus, even when egressing packet data that is ahead in line is shifting out toward a slow rate egress port; this slowing factor does not slow the speed at which the to-be egressed data (PdBx) can be shifted into the front-end raceway portion.

Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.

Abstract: In PCI-Express and alike network systems, back-up copies of recently sent packets are kept in a replay buffer for resending if the original packet is not well received by an intended destination device. A method for locating the back-up copy in the retry buffer comprises applying a less significant portion of the sequence number of a to-be-retrieved back-up copy to an index table to obtain a start address or other locater indicating where in the retry buffer the to-be-retrieved back-up copy resides. A method for skipping replay of late nullified packets includes deleting from the index table, references to late nullified packets.

Abstract: An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) replay data; and (3) to-be egressed data. Additionally, a shared free space (4) is managed between the storage areas of the (2) replay data and (3) the to-be egressed data. The to-be egressed data (PdBx) is allowed to enter into (to be written into) a front-end raceway portion of the integrated memory structure at a rate which can be substantially greater than that allowed for corresponding egressing packet data (PdUx). Thus, even when egressing packet data that is ahead in line is shifting out toward a slow rate egress port, this slowing factor does not slow the speed at which the to-be egressed data (PdBx) can be shifted into the front-end raceway portion.

Abstract: A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and a third node; a second impedance coupled between the second transmission line and the third node; and a low direct current reference voltage generator for generating a reference voltage applied to the third node. The first and second transmission lines may transmit complimentary signals. The first and second impedances may be symmetric or asymmetric. The first impedance may match the second impedance. The first and second impedances may, respectively, match the impedances of the first and second transmission lines. The first and/or second impedances may include a bidirectional switch, such as a transmission gate, to enable and disable the termination circuit.

Abstract: A phase difference detector having concurrent fine and coarse capabilities synchronizes operations of coarse and fine phase detectors. In one embodiment, clusters of fine timing markers are generated by delay stages of a delay locked loop. The K'th one of every cluster of J fine timing markers is designated as a coarse marker. A first timer determines which of J fine markers in a first cluster is closest to a rising edge of a reference signal. A second timer determines which of J fine markers in a second cluster is closest to a rising edge of a follower signal. A third timer determines how many coarse markers separate the rising edges of the reference and follower signals. Temporal displacement values obtained from the determinations of the first though third timers are combined to produce a phase displacement measurement signal of broad range and high precision across its operating range.

Abstract: A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.

Abstract: Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations.

Abstract: An intertwined test specification (ITTS) is used for controlling Automated Test Equipment (ATE) to apply a sequence of stimulus signals to a device under test (DUT) during a stimulus run and to validate returned response signals during a validation run. The ITTS has response validation scripts intertwined with stimulus invoking scripts where the response validation scripts are conditionally executed during the validation run but not during the stimulus invoking run. Response signals are logically associated with unique stimulus identification codes so that appropriate response signals can be matched with corresponding validation scripts even if the response signals are returned out-of-order to the ATE or to a response logging unit interposed between the ATE and the DUT.