Patents Represented by Attorney Trask Brit

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  • One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
    Patent number: RE36952
    Abstract: There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: November 14, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Paul S. Zagar, Kurt P. Douglas