Abstract: A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.

Abstract: Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.

Abstract: A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.

Abstract: Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A cover that is hinged to the card to normally cover one set of contacts can be rotated out of the way by hand when that set of contacts is being used.

Abstract: An impairment signal is introduced into an original visual signal, either electronically or optically, that is not noticeable in a display of the original visual signal but is noticeable in a copy made of the display by a camcorder or other camera, thereby discouraging the unauthorized recording of such displays. One application is to protect commercial movies against being copied in a theatre by a camcorder and distributed. In one form, the added impairment signal includes alternate transparent and dark regions moving across the screen or other display device. The degree of opacity of the dark regions and their speed of movement across the display are selected to make them unnoticeable in the theatre but highly noticeable in a camcorder copy of the movie that is made at a lower frame rate than that at which the movie is displayed.

Abstract: A cylindrical mirror or lens is used to focus an input collimated beam of light onto a line on the surface to be inspected, where the line is substantially in the plane of incidence of the focused beam. An image of the beam is projected onto an array of charge-coupled devices parallel to the line for detecting anomalies and/or features of the surface, where the array is outside the plane of incidence of the focused beam.