Abstract: A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active cell. The engineering change orders are registered with a pre-determined tool name, and it is detected and reported if another tool needs to be run to restore routing information. The active cell is not automatically saved after the engineering change orders are applied. Instead, a user must manually save the active cell after the tool is run. The tool can work with three different name spaces: Verilog, VHDL and Avant! Verilog.

Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.

Abstract: A semiconductor wafer is wetted with slurry by injecting the slurry into at least one channel which is provided in a wear ring, while the wear ring is holding the wafer and is pressed against a polishing pad. Preferably, the channel in the wear ring includes a plurality of outlets, and the outlets provide that the slurry can exit the wear ring and contact the polishing pad. Providing that the wear ring includes at least one channel and that slurry is injected into the channel during the polishing process provides that slurry is introduced between the wear ring and the polishing pad and this greatly increases the amount of slurry getting to the wafer.

Abstract: A method and control system for detecting harmonic oscillation in a chemical mechanical polishing process and reacting thereto, such as by taking steps to at least one of: 1) reduce or eliminate the harmonic oscillation; and 2) counter the noise which is associated with the harmonic oscillation. By reducing or eliminating harmonic oscillation, films with reduced structure strengths including low k dielectric films can be used. By countering the noise, the quality of the work environment is improved.

Abstract: The invention provides a method for OPC modeling. The procedure for tuning a model involves collecting cross-section images and critical dimension measurements through a matrix of focus and exposure settings. These images would then run through a pattern recognition system to capture top critical dimensions, bottom critical dimensions, resist loss, profile and the diffusion effects through focus and exposure.

Abstract: A method and control system for controlling the delivery of a source chemical by a carrier gas. The carrier gas is delivered to a vessel containing the source chemical, and a flow of source chemical and carrier gas is carried from the vessel along a flow line. A sensor is used to detect light absorption of the flow, and the flow is adjusted based on what is detected. The sensor provides that light is directed transversely through the flow line and that the intensity of the light which passes through the flow line is detected by a detector. The detector forwards an output signal to a signal processing unit which thereafter adjusts the flow based on what was detected. The light may be filtered. The flow line includes at least a portion which provides an optical window for allowing light to pass therethrough.

Abstract: An embodiment of the present invention provides a novel method which makes LVR to HVR registration possible by wrapping the X and Y scribes around each instance of each layer on both the LVR and HVR reticles; standard HVR reticles and LVR reticles will not align to one another due to registration and electrical test structures in the scribe being in different locations. Another embodiment of the present invention addresses the loss of die per wafer due to increased sribe area when using LVR and HVR reticles in the same set.

Abstract: A BISR scheme which provides that fuse blocks are shared between memories to reduce hard-BISR implementation costs. The scheme includes a plurality of memories serially connected to a fuse controller. A plurality of fuse blocks are also serially connected to the fuse controller. There are more memory instances than there are fuse blocks, and the fuse controller is configured to allow the fuse blocks to be shared between memories. Preferably, each fuse block includes fuse elements which can be programmed with the memory instance number which needs to be repaired. The fuse block reduces routing congestion and is preferably configured to provide the flexibility of assigning any fuse block to any instance that needs repair. The programmable fuse elements are preferably loaded into a counter (which is preferably part of the fuse controller) which ensures that the correct block information gets loaded into the corresponding memory instance.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: An improved method of using the Elmore Model to estimate the delay which is associated with the a clock buffer output. The improved method provides that the clock buffer output resistor is taken into account when the Elmore Model is used to calculate the delay. Also provided is a method of using the Elmore Model to estimate wire delay, where the method includes steps of calculating an approximate delay based on a distributed RC model, and using a capacitance value corresponding to the approximate delay in the Elmore Model to estimate the wire delay.

Abstract: A method for performing the edge clean operation on a semiconductor wafer. A laser beam is used to accurately clean the edge of the wafer. The wafer is clamped concentrically to a chuck and rotated at a selectable speed, preferably in the range of 10 rpm to 1,000 rpm. A laser beam of variable power is directed onto toward the edge of the wafer at an oblique angle through a nozzle through which an inert purge gas is simultaneously passed. The laser beam removes unwanted deposits at the edge of the wafer and the gas is used to blow away the residue and prevent slag buildup on other parts of the wafer. The process is preferably carried out in an exhausted chamber.

Abstract: Application of an extremely low K material by the application of a laminate onto a wafer. The laminate preferably contains alternating layers of low K material and etch stop layers, and could be applied by rolling the laminate onto the wafer. An anneal process can be utilized to bond the film to the wafer. Conventional photo masking and etching techniques are then used to open vias and line areas in the film, and to deposit the next copper layer on the wafer. Electro polishing can be used to planarize or remove residual copper. Thereafter, an etch step can be performed to remove the excess material between the copper lines to leave an ultra low K region between the copper lines. The next layer of low K film can then be deposited, and the process repeated for all subsequent metal layering.

Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.

Abstract: A silicon device which includes a silicon substrate and a bond pad array on the silicon substrate which is configured to be conductively connected to bond wire. The bond pad array consists of a plurality of bond pads which are vertically staggered on the silicon substrate. The vertical staggering allows the bond pads to be packed closer together on the silicon substrate, thereby reducing the horizontal space which is consumed by the bond pads on the silicon substrate, and thereby resulting in a reduction in die size. Preferably, the bond pads are also horizontally staggered on the silicon substrate, thereby allowing the bond pads to be spaced even closer together.

Abstract: A multiple layer power mesh design includes an L-shaped structure and a bow tie-shaped structure. The L-shaped structure provides a plurality of L-shaped power rails in each of four quadrants of the layer. The bow tie-shaped structure includes plurality of vertical power rails in each of a left and right triangularly-shaped portion of the layer. The vertical power rails of the bow tie-shaped structure provide and interface between the upper and lower quadrants of the L-shaped layer. The bow tie-shaped structure provides additional available space which can, for example, be used for routing signal traces. A T-shaped structure is also provided for use with the bow tie-shaped layer. The T-shaped layer provides for improved distances between the VDD and the VSS power rails.

Abstract: A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

Abstract: A system which includes a DMA (Direct Memory Access) interface and a MAC (Media Access Control) interface. A data FIFO and data burst information FIFO are disposed between the DMA interface and the MAC interface, and the system is configured to provide that information contained in the data burst information FIFO is used to discard unwanted data contained in the data FIFO, such that the unwanted data does not forward to the DMA interface. This facilitates fast and efficient data transfer, and avoids wasting (i.e. optimizes) DMA bandwidth. Additionally, this avoids or at least reduces the likelihood of FIFO overflow.

Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Abstract: A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application and exposure to define where a HBT device will be placed. Plasma etching the Silicon dioxide layer to define an undercut, epitaxially growing an Si—Ge layer and a Silicon layer, and continuing manufacture to form one or more bipolar and CMOS devices and define interconnect and passivation.

Abstract: A method to improve the resolution of a photolithography system by using one or more coupling layers between a photo resist and an anti-reflective coating. The coupling layer(s) compensate for a mis-match in indexes of reflection between the photo resist and anti-reflective coating and minimize the amount of energy which is reflected back into the photo resist, thereby improving the quality of the resulting image which is formed on the photo resist during the process.