Patents Represented by Law Firm Trial and Technology Law Group
  • Patent number: 6320489
    Abstract: The electronic surface mount package according to the present invention includes a one piece construction package having end walls, a side wall and an open bottom; a plurality of toroid transformers carried within the package by a soft silicone material wherein the toroid transformers each have wires wrapped thereon; a plurality of terminal pins molded within and extending from the bottom of the package wherein each of the pins extend through a bottom portion of the side wall and have a notched post upon which the wires from said transformers are wrapped and soldered thereon, respectively; and wherein the end walls have a first height H1 to form a standoff or safe guard between the foot seating plane of the package and the terminal pins; and wherein the outer portion of the side wall extends between the end walls such that the side wall has a second height H2 which is less than said first height H1.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: November 20, 2001
    Assignee: Halo Electronics, Inc.
    Inventors: Peter Lu, Jeffrey Heaton, James W. Heaton, Peter Loh Hang Pao, Robert Loke Hang Lam, Tsang Kei Sun
  • Patent number: 6297721
    Abstract: An electronic surface mount package provides a one piece construction package (with an open bottom) with one or more terminal pins molded into the package. Each of the pins have a notched post upon which a wire is wound which is from a toroid transformer carried within the package. Each of the posts are notched so their respective wires are separate from one another so as to prevent arcing. The case is opened at the bottom which prevents harm from expansion or cracking. A reinforcement beam is located laterally across the bottom of the package to provide mechanical strength for the case.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: October 2, 2001
    Assignee: Halo Electronics, Inc.
    Inventors: Peter Lu, Jeffrey Heaton, James W. Heaton, Tsang Kei Sun, Peter Loh Hang Pao, Robert Loke Hang Lam
  • Patent number: 6297720
    Abstract: An electronic surface mount package provides a one piece construction package (with an open bottom) with one or more terminal pins molded into the package. Each of the pins have a notched post upon which a wire is wound which is from a toroid transformer carried within the package. Each of the posts are notched so their respective wires are separate from one another so as to prevent arcing. The case is opened at the bottom which prevents harm from expansion or cracking. A reinforcement beam is located laterally across the bottom of the package to provide mechanical strength for the case.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: October 2, 2001
    Assignee: Halo Electronics, Inc.
    Inventors: Peter Lu, Jeffrey Heaton, James W. Heaton, Tsang Kei Sun, Peter Loh Hang Pao, Robert Loke Hang Lam
  • Patent number: 6275991
    Abstract: A television remote control unit including an IR (infra-red) transmitter with integral magnetic stripe ATM type credit card reader and method therefor for transmitting IR signals to a remote interactive location such as a television set or a TV cable remote control box. The remote control unit permits the user to swipe a credit card through the credit card reader so as to generate credit card transaction signals for transmission to the remote interactive locations. The remote control unit can be used in an interactive environment such as a hotel casino, a cable TV home shopping network, or an off track betting (OTB) environment.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: August 14, 2001
    Assignee: FCA Corporation
    Inventor: Dan Erlin
  • Patent number: 6271598
    Abstract: A flip chip on chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, the present invention provides a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: August 7, 2001
    Assignee: Cubic Memory, Inc.
    Inventors: Alfons Vindasius, Marc E. Robinson, William R. Scharrenberg
  • Patent number: 6255726
    Abstract: An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: July 3, 2001
    Assignee: Cubic Memory, Inc.
    Inventors: Alfons Vindasius, Kenneth M. Sautter
  • Patent number: 6202468
    Abstract: The present invention relates to a method of determining the relative proportions of gases in a mixture, such that the relative proportions of N gases are determined using N-1 sensors, not all of which are specific to a particular gas. In the preferred embodiment, oxygen and carbon dioxide are measured in the presence of nitrogen by measuring magnetic susceptibility and speed of sound. The described method of gas analysis leads to very fast response times and exceptional stability, making the technology suitable for breath-by-breath analysis of respired air. Notably, the method does not require high-temperature components, electrochemical cells, or consumable components.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: March 20, 2001
    Assignee: Life Measurement Instruments
    Inventors: Philip Dempster, John Payne
  • Patent number: 6199277
    Abstract: The present invention provides a bake carbon flue straightener for straightening a flue wall of an anode baking surface from a deformed or bowed position to a straight or normal position. The flue straightener includes a plurality of remotely controlled and independently actuated hydraulic cylinders mounted on a plurality of elevations space apart at equal distances from each other, a steel frame for supporting hydraulic cylinders, such that each of the elevations of the hydraulic cylinders are coupled to a continuous length of extendable solid push plates for extending the push plates to the deformed or bowed flue wall so as to push or straighten with equally distributed forces the deformed or bowed flue wall back to the straight or normal position.
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: March 13, 2001
    Assignee: Century Aluminum of West Virginia, Inc.
    Inventor: Michael Massile
  • Patent number: 6192053
    Abstract: An Adjacency Detection Protocol (ADP) whereby a node in a wireless network may collect information about its neighbors. The collected information enables the establishment of link layer connectivity between a node and its neighbors and also is useful for translating network layer addresses into link addresses. The collected information finds further use in preventing medium contention among adjacent nodes and in handling collisions.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: February 20, 2001
    Assignee: Wireless Networks, Inc.
    Inventors: Dean Angelico, James Alan Hayes
  • Patent number: 6188126
    Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment, includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: February 13, 2001
    Assignee: Cubic Memory Inc.
    Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
  • Patent number: 6177296
    Abstract: A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: January 23, 2001
    Assignee: Cubic Memory Inc.
    Inventors: Alfons Vindasius, Kenneth M. Sautter
  • Patent number: 6171151
    Abstract: An isolation module for an RJ-45 modular jack provides isolation and noise control and reduction for the RJ-45 modular jack. The RJ-45 modular jack includes a front surface having an opening for receiving a corresponding modular plug. The RJ-45 modular jack further includes a plurality of electrical fingers arranged in a spring bias fashion within the opening in the front surface for making electrical contact with a modular plug. The RJ-45 modular jack includes a series of sockets or slots along the back surface of said modular jack such that the electrical fingers extend to the back side of the modular jack and terminate in a reverse bent fashion to form a socket or clip portion within a respective socket or slot.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: January 9, 2001
    Assignee: Halo Electronics, Inc.
    Inventors: Peter Lu, Jeffrey Heaton, James W. Heaton, Peter Loh Hung Pao, Robert Loke Hang Lam, Tsang Kei Sun
  • Patent number: 6169789
    Abstract: This invention generally relates to a system level scheme utilizing an intelligent keyboard, hereafter called an Intellikeyboard, which can operate as a universal compute, command, and control module that interfaces either through wired or wireless means with a number of intelligent appliances, personal computers, work-stations, servers, televisions, printers, smart devices, intelligent devices, telephones, or other devices. The Intellikeyboard has the ability to transmit and receive voice, text, graphics, and other data through either wired or wireless means. The Intellikeyboard may work in tandem with a local or network server to perform standard computing functions, serve as a command and control unit, perform standard telephony functions, transmit and receive electronic mail, voice mail, video, and audio. The invention also anticipates the need for multichannel and sequential/simultaneous tasking and interface with numerous intelligent appliances and devices.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: January 2, 2001
    Inventors: Sanjay K. Rao, Sunil K. Rao, Raman K. Rao
  • Patent number: 6134118
    Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: October 17, 2000
    Assignee: Cubic Memory Inc.
    Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
  • Patent number: 6124633
    Abstract: An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: September 26, 2000
    Assignee: Cubic Memory
    Inventors: Alfons Vindasius, Kenneth M. Sautter
  • Patent number: 6098278
    Abstract: A flip chip on chip method for forming a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of the first flip chip to form an electrical connection between the first flip chip and the second flip chip. In another preferred embodiment, a method for forming a flip chip assembly including a plurality of semiconductor chips where the plurality of chips are vertically interconnected on top of one another to form an electrically interconnected stack of chips; a flip chip directly connected to the top chip of the stack of chips; and electrically conductive epoxy means disposed between said flip chip and said top chip to form an electrical connection between the flip chip and the top chip.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: August 8, 2000
    Assignee: Cubic Memory, Inc.
    Inventors: Alfons Vindasius, Marc E. Robinson, William R. Scharrenberg
  • Patent number: 6080596
    Abstract: A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: June 27, 2000
    Assignee: Cubic Memory Inc.
    Inventors: Alfons Vindasius, Kenneth M. Sautter
  • Patent number: 6079778
    Abstract: A padded chair cover according to the present invention uniformly covers virtually any style of fixed chair. The chair cover includes a padded foam-type structure to cover a chair. The padding is made of a relatively rigid commercially available foam. The rigidity of the foam allows the chair cover to maintain its shape regardless of the kind or shape of chair it covers. Thus a mismatched group of chairs can be covered with the same style of chair cover producing a uniform set of chairs with a formal upholstered look.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: June 27, 2000
    Inventor: Nafiseh Lindberg
  • Patent number: 6050319
    Abstract: The present invention provides a non-round container labeling machine and corresponding method. In one embodiment, the present invention provides a labeling machine for applying a label to a non-round container or article where the non-round article has a series of corners located about its surface. The labeling machine according to the present invention includes a rotatable vacuum drum, the drum including engaging means for rotatably engaging the corners of the non-round articles. The labeling machine includes a label associated with the engaging means and a resilient roll on pad means. The labeling machine further includes means for rotating the non-round article between the drum and roll on pad means wherein the engaging means engages a first corner to rotate the article between the drum and the pad means such that the drum generates a torque which rotates the article as the drum rotates and which compresses the roll on pad means such that the pad means stores compressed torque energy.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: April 18, 2000
    Assignee: Trine Labelling Systems
    Inventor: Gaylen R. Hinton
  • Patent number: 6046051
    Abstract: The present invention provides a single-use electronic device and test card for use therein which performs a coagulation or lysis assay of a blood sample. The device includes a housing having an exterior surface and defining an interior area and means for receiving the sample through the housing into the interior space. A non-porous substrate is positioned within the interior space for receiving the sample thereon. A reagent accelerates the coagulation of the sample and is positioned on the substrate and in contact with the sample. Optionally, an electroactive species may also be reacted with the sample. The device also includes means for measuring the viscosity of the sample and generating an electrical signal which correlates to a curve of the coagulation/lysis assay.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: April 4, 2000
    Assignee: Hemosense, Inc.
    Inventor: Arvind N. Jina