Abstract: A method for scanning and sorting documents which employs data not found on the document to make the sorting decision. Provision is also made for correcting misread information with the most probable correct data so that the scanning and sorting process may continue uninterrupted. In one form, the method comprises the steps of: (a) reading first data from a document by optical character recognition; (b) accessing second data which contains a list of valid first data; (c) determining if said data contains an error based on said second data; (d) accessing third data if said first data contains an error, said third data containing a probable correction of said first data; (e) changing said first data to equate with said third data; (f) retrieving fourth data from a data file based upon said first; (g) sorting said document based upon said fourth data.

Abstract: Generally, and in one form of the invention, a p-n junction diffusion barrier is disclosed comprising a first semiconductor layer 28 of p-type conductivity, a second semiconductor layer 32 of n-type conductivity and a third semiconductor layer 30 of p-type conductivity disposed between the first and second layers, the third layer being doped with a relatively low diffusivity dopant in order to form a diffusion barrier between the first and the second semiconductor layers.Other devices, systems and methods are also disclosed.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: A high speed, low power parallel analog-to-digital converter (100) with comparator (C.sub.j) having sense amplifiers operating with low power, high speed and a ROM encoder (130) also operating in low power, high speed regime.

Abstract: An integrated circuit buffer includes an input differential amplifier with a first current source transistor and a network with second current source transistors and cascode transistors loading the differential amplifier. Further included is a network having transistors and a resistance connected to introduce bias voltages to the first and second current source transistors to set a common mode level for the cascode transistors wherein the bias voltages are generated by the network independently of said common mode level. The bias voltages establish a respective lesser current from the first current source transistor and a greater current from the second current source transistors connected to the cascode transistors. Other circuits, devices, systems and methods are also disclosed.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: Generally, and in one form of the invention, a multiple layer collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14.

Abstract: Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. Next, an i-layer 16 is grown over the first surface, over which an HFET electron donor layer 18 of the first conductivity type is grown, the electron donor layer 18 having a wider energy bandgap than the i-layer. Subsequently, an HFET contact layer 20 of the first conductivity type is grown over the HFET donor layer 18. Next, the HFET contact 20 and donor 18 layers are etched away over the HBT subcollector region 12, after which an HBT base layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base layer 22.

Abstract: A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array (86). The array (86) simultaneously outputs two data words in response to two read addresses to sense amps (94) and (98). Data can be written into the memory by storing it in a data latch (100) and addressing it with a separate write address. The separate write address is latched in a write address (108) which is enabled on the rising clock edge by control circuit (114).

Abstract: A polysilicon self-aligned transistor has a polysilicon layer (24) with a cavity (30) formed therein. To form the polysilicon layer (24) with a cavity (30), a thin seed layer (14) is disposed over an epitaxial layer (11a). Dielectric layers (16, 18) are formed over the seed layer (14), and are subsequently etched to define the polysilicon layer (24) and the cavity (30). The cavity (30) is defined by a dielectric plug (22). The exposed seed layer (14) is used to selectively grow the polysilicon layer (24). Thereafter, the dielectric plug (22) is removed to form the cavity (30) through which the base (32) is implanted into the substrate (12) and the emitter (36) is formed.

Abstract: A method and circuitry for reducing noise is provided. The circuit receives a digital data signal at its input (26). The signal is input to a magnitude evaluator (28) and a pass/squelch circuit (30). Magnitude evaluator (28) samples the digital signal and controls an integrator (36) according to the magnitude of each of the samples. Integrator (36) averages the magnitudes over time. If the signal is a noise signal, integrator (36) toggles a switch (40) to activate pass/squelch circuit (30) to squelch the digital data at its input (29). If the signal is a valid signal, then integrator (36) toggles switch (40) to deactivate pass/squelch circuit (30) to allow the digital data to pass therethrough to destination device (44).

Abstract: An infrared or x-ray imaging CCD array, including deep trench isolation (56) for capturing electron carriers formed deep in the substrate (46) as a result of long wavelength radiation or high energy particles. In virtual phase CCD circuits, the trench has formed on the sidewalls thereof a diffusion (58, 60) defining a vertical conductor for allowing hole carrier conduction between the substrate (46) and the virtual phase electrode (38).

Abstract: In one embodiment of the invention, a method for fabricating a virtual phase image sensor is disclosed comprising the steps of forming a semiconductor substrate of a first conductivity type, forming a buried channel region of a second conductivity type in the substrate, forming a virtual gate of the first conductivity type at a surface of the buried channel region, implanting channel stop regions of the first conductivity type in the virtual gate, the channel stop regions contacting the buried channel, and forming a conductive contact on an upper surface of the channel stop regions wherein the conductive contact is additionally coupled to the substrate.