Abstract: Switched capacitor notch filter circuits are disclosed.

Abstract: A class AB output stage includes first (MP) and a second (MN) output transistors having sources coupled to first (VDD) and second reference voltages, respectively, drains coupled to an output (13), and gates coupled to first (11A) and second (12A) conductors, respectively. Portions of first (IIN1) and a second (IIN2) input currents are sourced via a first input conductor (11) and a second input conductor (12), respectively, into and from sources of first (M2) and second (M4) transistors, respectively. Gates of the first (M2) and second (M4) transistors are coupled to the first and second conductors, respectively. First (VrefP) and second (VrefN) bias voltages are applied to gates of third (M1) and fourth (M3) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.

Abstract: According to one embodiment of the invention, a method of fabricating ball grid array packages includes providing a substrate, providing a ball film that includes a plurality of metal balls movably contained within respective slots of a thin film, coupling the metal balls to the substrate, and removing the thin film from the metal balls.

Abstract: System and method for write current drivers for inductive heads used in mass storage drives. A preferred embodiment comprises a write current circuit coupled to an inductive write head, a MOS transistor boost circuit and a matching circuit, both coupled to the write current circuit. The write current circuit provides a first current to the inductive write head, while the MOS transistor boost circuit provides a second current for a specified duration to the inductive write head when the MOS transistor boost circuit receives a control signal. The matching circuit selectively decouples a resistive element from the inductive write head when it receives the control signal. The MOS transistor boost circuit can accelerate the transition in a switching of the polarity of the write current and the matching circuit helps to reduce ringing without negatively affecting the speed of the polarity switching by decoupling when the second current is provided.

Abstract: An integrated circuit (22) having a serial interface (25) with improved access times is disclosed. The serial interface (25) includes a serial output port arranged as a shift register of flip-flop stages (321 through 32n) and a last output latch stage (320). The last output latch stage (320) includes an integral output buffer (33), and as such is constructed differently from the other output flip-flops (321 through 32n), which include master and slave latches. No external output buffer is then required; this last output latch stage (320) directly drives the output terminal and the external serial data line (SDATA).

Abstract: A thin film resistor structure includes a plurality of thin film resistor sections. Conductive vias (5) are disposed on a first end of each of the thin film resistor sections, respectively. The first conductor (2) is connected to the vias of the first end, and a second conductor (3) is connected to vias on a second end of each of the thin film resistor sections. A distribution of a parameter of a batch of circuits including the thin film resistor structure indicates a systematic error in resistance values. Based on analysis of the distribution and the circuit, or more of the vias are individually moved at the layout grid level by a layout grid address unit to reduce the systematic error by making corresponding adjustments on a via reticle of a mask set used for making the circuits. Expensive laser trimming of thin film resistors of the circuit is thereby avoided.

Abstract: The present invention achieves technical advantages as a preamplifier write driver (10) having a varying common-mode output voltage. This varying common-mode output voltage also adjusts the derivative of the common-mode voltage, which is proportional to the amount of current coupled onto the MR head through parasitic capacitance. Currents of a first circuit (Q0,Q3) and a second circuit (Q1,Q2) are matched to overcome process variations and modeling errors. A pair of transresistance amplifiers (16) are driven by control lines (14) to achieve these matched currents.

Abstract: A metal structure (100) for a contact pad of a semiconductor, which has interconnecting traces of a first copper layer (102). The substrate is protected by an insulating overcoat (104). The first copper layer of first thickness and first crystallite size is selectively exposed by a window (110) in the insulating overcoat. A second copper layer (105) of second thickness covers conformably the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The distance a void can migrate from the second layer is smaller than the combined thicknesses of the first and second layers. A nickel layer (106) is on the second copper layer, and a noble metal layer (107) is on the nickel layer.

Abstract: According to one embodiment of the invention, a system used in auto-boating includes a tape substrate supported by a boat. The tape substrate includes a pair of lateral edges parallel to one another and each having respective first and second ends, and a pair of longitudinal guide strips parallel to one another. One of the longitudinal guide strips extends between the respective first ends of the pair of lateral edges and the other longitudinal guide strip extends between the respective second ends of the pair of lateral edges. The tape substrate also includes a plurality of die attach regions disposed within the area defined by the pair of lateral edges and the pair of longitudinal guide strips. The system further includes a boat clip coupled to the boat such that the tape substrate is sandwiched between the boat and the boat clip. Each longitudinal guide strip includes a pair of tabs disposed at opposite ends thereof such that each tab extends beyond a respective one of the lateral edges.

Abstract: According to one embodiment of the invention, a mold tool for packaging integrated circuits includes a first mold press die including a first non-planar surface and a second mold press die including a second non-planar surface. The first and second non-planar surfaces form the upper and lower surfaces of a mold cavity when the first and second mold press die are engaged. The mold tool also includes a bright TiN coating disposed on the first non-planar surface. The bright TiN coating operates to decrease residue on the first non-planar surface from a mold compound.

Abstract: A system and method to provide a slow start up voltage, such as that can slowly ramp up or down by cyclically coupling a pair of associated energy storage devices, such as capacitors, during a start-up phase. The cyclic coupling of the capacitors, in conjunction with causing a change in charge associated with a first of the storage devices, results in incremental changes in the energy of the second energy storage device over a plurality of cycles. The energy associated with the second storage device can be used to control output circuitry that provides a desired ramp output signal.

Abstract: A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a plurality of contact pads on a PCB. At least one of a plurality of solder balls of an IC device are then onto the at least one of the plurality of contact pads on the PCB. The temperature is then increased to reflow the solder paste. The IC device is then pulled away from the PCB as a function of a geometric shape of the IC device and held in a new position upon reflowing the solder paste to transform the at least one of the plurality of solder balls and the reflowed solder paste into a high shear strength solder joint structure. The reflow temperature is then lowered to room temperature to attach the high shear strength solder joint structure to the at least one of the plurality of lands on the PCB.

Abstract: An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.

Abstract: A communications system 400 includes a transmitter 410 that transmits information to a receiver 440 over communication channels 420 and 430. The receiver 440 determines reconfiguration transceive parameters, ack/comply timing information and implementation timing information and provides this information to the transmitter 410, e.g., over an OAM channel 420. The transmitter 410 returns an ack/comply to the receiver 440, e.g., over a lower layer OAM channel 430, at a time in accordance with the ack/comply timing information. If the acknowledgment indicates acceptance of the reconfiguration transceive parameters, both the transmitter 410 and the receiver 440 implement the reconfiguration transceive parameters at a time in accordance with the implementation delay timing information.

Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).