Abstract: A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.

Abstract: An interconnect structure and its method for fabrication each employ an interconnect formed over and adjacent an active region of a semiconductor substrate. A gate electrode is also formed over the active region. Spacer layers are formed adjoining the interconnect and the gate electrode. A spacer layer adjoining the interconnect is removed and a bridging silicide conductor layer is formed bridging a top surface and a sidewall surface of the interconnect with a surface of the active region.

Abstract: A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a second dielectric; forming a second dielectric insulator over the first dielectric insulator; forming a second opening in the second dielectric insulator overlying and communicating with the first opening; and, filling the first and second openings with a conductive material to electrically communicate with the conductive area.

Abstract: A tungsten plug deposition process that incorporates a dual-step nucleation method and the semiconductor structure formed by such method are disclosed. In the tungsten plug deposition process, a first nucleation layer is formed in the via openings in the semiconductor substrate by flowing a reactant gas mixture of WF6/SiH4 at a first mix ratio between 1:1 and 1:10 in a chemical vapor deposition chamber. A second nucleation layer is then formed on top of the first nucleation layer by flowing a reactant gas mixture of WF6/SiH4 at a second mix ratio between 2:1 and 5:1 into the chemical vapor deposition chamber. A total thickness of less than 500 Å for the first and second nucleation layers is normally sufficient. The first nucleation layer formed is a silicon rich layer, or a WSix layer, while the second nucleation layer is substantially W.