Abstract: A method of simulating dropping of a box on an impact specimen is disclosed. An illustrative embodiment of the method includes providing an impact head simulating a corner of a box, providing an impact specimen, causing impact of the impact head with the impact specimen and examining the impact specimen. A method of simulating dropping of a box on an impact specimen is also disclosed.

Abstract: A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon oxide layer; dry etching in a first etching process to form a patterned hardmask opening for etching an STI opening; dry etching in a second etching process the semiconductor substrate to form an upper portion of an STI opening to form a polymer layer along sidewall portions of the STI opening; and, dry etching in a third etching process the STI opening to form rounded bottom corners and rounded top corners.

Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.

Abstract: A novel process for re-distributing a barrier layer deposited on a single damascene, dual damascene or other contact opening structure. The process includes providing a substrate having a contact opening structure and a metal barrier layer deposited in the contact opening structure, re-sputtering the barrier layer by bombarding the barrier layer with argon ions and metal ions, and re-sputtering the barrier layer by bombarding the barrier layer with argon ions.

Abstract: A method for polishing a material layer on a semiconductor wafer to a desired target layer thickness. The method includes calculating a compensated removal rate based on the thickness of material to be removed from a material layer on the wafer according to a standard value; the current material removal rate of the CMP apparatus; and the offset thickness, which equals the difference between the thickness of the material layer which would be attained using the current material removal rate and the target thickness for the material layer. The calculated compensated removal rate is then programmed into the controller for the CMP apparatus, which polishes the material layer at the calculated compensated removal rate to achieve the desired target layer thickness for the layer.

Abstract: A method for forming a patterned silicon-containing layer is disclosed. The method includes providing a substrate, providing a polysilicon layer on the substrate, providing a hard mask layer on the polysilicon layer, patterning and etching the hard mask layer and etching the polysilicon layer according to the pattern of the hard mask layer using a fluorine-containing etchant gas. The resulting sidewall profile of the etched polysilicon layer is substantially straight, uniform and devoid of a necking or notched configuration.

Abstract: A calibration cassette pod for robot teaching and a method of using the calibration cassette pod are described. In the calibration cassette pod, a cassette pod body and a cassette pod door are first provided wherein the cassette pod body is constructed of a top panel, a bottom panel, two side panels and a front panel to enclose a cavity therein. A first plurality of ribs is formed on an inside surface of the cassette pod body, each having a predetermined depth sufficient to support an edge portion of a wafer. An optical detector housing is mounted on an opening in the front panel and is adapted for receiving an optical detector therein. An optical detector that includes a light emission source and a photo diode receiver for determining the position of the edge portion of the wafer is mounted in the optical detector housing.

Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

Abstract: A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the ion implant methods implants a portion of an intrinsic base region interposed between an extrinsic base region and a polysilicon emitter layer with an amorphizing non-active dopant. A second of the ion implant methods implants the polysilicon emitter layer with an active dopant to form a doped polysilicon emitter layer. The polysilicon emitter bipolar transistor is fabricated with enhanced performance.

Abstract: A lithographic apparatus for forming a patterned resist layer and a method for forming a microelectronic product both employ a lithographic exposure tool controller designed to: (1) receive input data for at least one non-environmental variable that influences an exposure dose when forming a patterned resist layer from a blanket resist layer while employing a lithographic exposure tool; and (2) determine the exposure dose for forming the patterned resist layer from the blanket resist layer while employing the input data. The apparatus and method provide for forming the microelectronic product with enhanced dimensional control.

Abstract: In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

Abstract: Determining the maximum number of dies that fit on a semiconductor wafer is disclosed. The x- and y-coordinates of an initial starting position on a semiconductor wafer are determined. The delta-x and delta-y offsets for subsequent starting positions are also determined. Starting at a current position equal to the initial starting position, the following is repeated for each of a predetermined number of times. First, the semiconductor wafer is covered with fields. Second, the number of dies that are completely covered by the semiconductor wafer is counted. Third, the current starting position is increased by the delta-x and the delta-y offsets. Once this has been repeated, the actual starting position is set as the current starting position at which the number of dies completely covered by the semiconductor wafer is maximized.

Abstract: A back-end method for photomask making generally includes the steps of inspecting a photomask and repairing each defect on the photomask. The step of inspecting the photomask preferably comprises a defect finder mark implementation routine. In general, when inspecting the photomask for defects, the defect finder mark implementation routine deposits a defect finder mark on the photomask via a mark installer (not shown) included with a mask marking inspection system. Deposition of the defect finder mark includes establishing a location that is adjacent to the defect and establishing a size that is detectable by a mask repair device (not shown). By deposition on the photomask, the defect finder mark reliably facilitates location of the corresponding defect despite variations in image resolution and stage movement between the mask marking inspection system and the mask repair device.

Abstract: A static resistant reticle comprises a substrate and a patterning layer and is covered by an antistatic conductive film of quaternary amine (R4N)+Cl?. A pellicle structure comprising an optically transparent membrane tightly stretched on a frame is also coated by an antistatic electro conductive film of a similar material. The reticle with the pellicle form a shielded structure isolating the reticle from ESD.

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract: Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract: A multi-point calibration standards and a method of fabricating calibration standards which are used to quantify the dose or concentration of a dopant or impurity in a silicon matrix. The calibration standards include a set of calibration standard wafers for each dopant or impurity to be quantified. On each calibration standard wafer in the set is provided a silicon matrix incorporated with one of various concentrations, by weight, of the dopant or impurity in the silicon. The atomic concentration of the dopant or impurity in the silicon on each wafer in the set is measured. A calibration curve is then prepared in which the silicon/dopant or silicon/impurity ratio on each calibration standard wafer in the set is plotted versus the atomic concentration of the dopant or impurity in the silicon on the wafer.

Abstract: A method for in-situ reduction of volatile residual contamination on a semiconductor process wafer following a plasma etching process including providing an ambient controlled chamber for accepting transfer of a semiconductor process wafer under controlled ambient conditions following a plasma etching process; providing a heat exchange surface disposed with the ambient controlled chamber in heat exchange relationship with means for heating the heat exchange surface; transferring a semiconductor process wafer having volatile residual contamination under controlled ambient conditions to the ambient controlled chamber; mounting the semiconductor process wafer in heat exchange relationship with the heat exchange surface; and, heating in-situ the heat exchange surface for a time period to thereby heat the semiconductor process wafer to vaporize the volatile residual contamination on the semiconductor process wafer while simultaneously removing a resulting vapor from the ambient controlled chamber.