Abstract: Actual customer data is routed through a composite muldem which comprises a high speed section and a plurality of low speed sections with the signals being switched or transferred between the high speed and low speed sections all at a common frequency. This same customer data is then tested by a bit by bit comparison circuit which tests the data after it is split, rerouted in various datapath configurations and compared in a logical fashion to first detect datapath failure and then isolate the failure to a specific part of the composite muldem by a set of logical deductions.

Abstract: A way to reduce costs in a communication network is to use through-repeaters for any signal channels that do not need to have data dropped or inserted at a given site. This however complicates any protective switching involved to bridge failed data channels. The present system incorporates a master computer at one end of the switching network which communicates to a plurality of slave computer controllers at all the remaining sites having drop and insert channels whereby it can maintain an up to date table of the system configuration and thereby use segments of the protection channel to bridge various failed portions of the entire system.

Abstract: An interface device for use between a North American PCM channel bank and a CCITT PCM channel bank which allows data to stay in digital format rather than being converted to voice frequency. The interface takes care of not only the completely different serial data rates, but the different transfer characteristics of the channel data words. Synchronization is obtained by dividing the serial data stream into enough channel banks so that there is less than one-half cycle time period difference between the frequency of the incoming and outgoing data streams for one cycle of channel data words.

Abstract: To produce bundles from strip, the strip is withdrawn from an uncoiler or coil and slit into a number of narrow strips that are supplied parallel and separated by about 2 mm to a winding point. The strip is wound at the winding point into bundles with a sheet-like or film-like insert that extends over the total width of the strips being supplied adjacent to each other also being wound in between the individual layers of the bundles. When the resultingly wound strip are unwound, the insert between the bundle at one end of the composite coil and the rest of the composite coil is separated in such a way that a strip of insert is removed along with a strip of metal from the composite coil and wound or coiled separately from the metal strip. The composite coil made up of individual parallel metal strips with the insert wound between them can be conveniently handled for conveying and storage at both its surface and side edges.

Abstract: The present invention uses digital values of MSK-like waveshapes which can be stored in a storage media such as a ROM and then output in a prescribed fashion such as in phase quadrature through the use of an addressing technique to the ROM. The digital values, each of N bits, are then multiplied in quadrature times a data representative signal which is divided into phase quadrature components. These N+1 bit products are summed to produce a composite digital signal representing analog bipolar values. A digital-to-analog conversion provides the modulated analog output signal.

Abstract: A block diagram and concept approach for use in conjunction in decision feedback equalization of providing positive decision feedback to enhance the amplitude of the present bit at the same time as delayed intersymbol interference feedback is provided to provide a larger eye pattern in the compensated and equalized output signal as compared to that obtained without the positive decision feedback pulse amplitude enhancement.

Abstract: The present invention provides error checking for data dependent coding circuitry which checking is complicated by a considerable amount of circuitry which is activated only when the incoming data conforms to specific requirements (i.e., three or more consecutive logic zeros). Except for these occurrences, the output from the coding circuitry is straightforward representation of the nonreturn to zero input data. The present invention uses a straightforward detecting circuit to normally pass the data and a data compare circuit which compares the output of the detector with the output of the data dependent circuitry except for times when the specific condition of three consecutive logic zeros occurs. At that time, the data compare circuitry checks to make sure that both the code detector and the encoding circuit have detected the occurrence of this condition.

Abstract: A slightly flexible and generally C-shaped cable support apparatus for quick attachment and detachment from a sheet material support structure to which a plurality of cables can be tied using cable ties and which locks in place after the cable support apparatus is temporarily deformed and moved laterally into position. Removal is accomplished by temporarily deforming the support apparatus and removing in the opposite direction from the insertion. The holding means used in the insertion process are devised to accept different thicknesses of sheet material support structure. An edge of the C-shaped portion of the cable support apparatus is designed to reduce cable insulation damage on sharp edges of the sheet material by extending over and covering same.

Abstract: A circuit approach is illustrated for simplifying a count divider circuit by applying selected outputs of the counter to a J-K flip-flop as input to the J-K terminals whereby a comparatively high speed response is returned for presetting the counter as compared to the prior art approach which either required much more circuitry or intolerable time delays.

Abstract: By exchanging the position of the input and output resonator means relative to other resonator elements in a mechanical filter, the lengths of the bridging wires used to control the steepness of the bandpass characteristic of the filter can be reduced. Reducing the length of the bridging wires reduces both flexural spurious mode problems and extensional coupling variation problems.

Abstract: Monitoring or error checking equipment for use with multiplexing circuitry at the transmission end of a communication line is disclosed which accomplishes a large reduction in circuitry by using transmitter generated low speed timing signals and clock signals to demultiplex the output data into nonsymmetrical or timing irregular data. The plurality of channels of nonsymmetrical data are then each checked for parity and framing pulses as well as clock activity by time multiplexed switching equipment on a cyclical basis.

Abstract: If the timing of detection of an analog signal, by an A/D converter, with respect to its theoretical value is optimum, the most significant error bit output by the A/D converter will integrate to a zero value. The present invention takes the information indicative of the most recent history of amplitude variation of the analog signal to logically modify (affect polarity) the most significant error bit and apply it to an integrator. The integrated value is used to adjust a variable time delay clock circuit use in determining the detection time in the A/D converter.

Abstract: The overhead format for DS1C data must be removed and the data broken into two DS1 format data signals before being transmitted over DS2 or DS3 transmission lines. The present invention demonstrates a method whereby the stuff bit code for appropriate frames of a high speed transmission line can be violated and remotely detected whereby the signal is looped back at the destination end of the desired signal whether the remote signals are in the DS1C or DS1 data format.

Abstract: When an A/D converter is converting a multilevel analog signal into a plurality of distinct digital words, it needs to have a very accurate reference voltage which is tied to the voltage levels of the analog signal being converted for high accuracy. The present invention takes the most significant bit and an error bit signal from the analog-to-digital converter and logically combines these signals in such a way that error feedback signals are generated which are integrated over the long term and used to adjust the reference voltages supplied to the analog-to-digital converter wherein the feedback error signals average to zero.

Abstract: A phase detection function is obtained by performing two series retiming operations on a data input signal in accordance with a local clock and exclusive OR'ing the signals involved in the two retiming operations. The first exclusive OR'ing provides a variable pulse width signal and the second exclusive OR'ing provides a fixed pulse width signal which may be used as a reference. The combination of the two signals can then be used to provide an indication of phase of the clock with respect to the data. By taking the phase detected signal and supplying it in integrated format to a VCO and using the output of the VCO to provide the clock input to the retiming means, a circuit is provided which provides not only data regeneration, but also clock recovery from the data input and assures that the leading edge of the recovered clock is centered between positive going and negative going transitions of the data to be regenerated.

Abstract: An adjustable slope equalizer is disclosed for maintaining a predetermined output level at a predetermined frequency. An equalizer comprises: an adjustable input means; a first voltage divider means having an output and having an input operatively connected to the low impedance input means; a second voltage divider means having an output and having an input operatively connected to the low impedance input means; an adjustable high impedance means having an output and having at least two inputs operatively connected to the outputs of the first and second voltage divider means; and a SAG correction means operatively connected to the output of the adjustable high impedance means. The output of the SAG correction means has the predetermined output level at the predetermined frequency for any setting of the adjustable high impedance means.

Abstract: A multilevel data base memory structure for use by the processor control of each of a plurality of interconnected telecommunication switching systems so that communications between any two of the systems can be established with minimal interaction by the users. A comprehensive directory number plan provides for the allocation of blocks of at least one hundred directory numbers (i.e. 2400-2499) to the stations or features of each switching system. For those directory numbers serviced by a switching system the thousands/hundreds digits are utilized as addresses of locations of the memory structure first table level, the contents of which are pointers to various sections of a second table level. Within each such section the tens/units digits are used as addresses to define a location having stored therein an ultimate system function representative of, for instance; a standard call, conference call, speed dial . . . etc.