Patents Represented by Attorney, Agent or Law Firm Valerie G. Dugan
  • Patent number: 6303994
    Abstract: A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: October 16, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Hougong Wang, Gongda Yao
  • Patent number: 6299689
    Abstract: A method and apparatus for reflowing a material layer is provided. The inventive method introduces into a reflow chamber a material which is at least as reactive or more reactive than a material to be reflowed (i.e., a gettering material). Preferably the gettering material is sputter deposited within the reflow chamber while a shield prevents the gettering material from reaching the material layer to be reflowed. The shield may be coupled to, or integral with a clamp for clamping a wafer (containing the material layer to be reflowed) to a wafer support provided sufficient venting exists so that contaminants degassed from the wafer may flow to the region between the sputtering target and the shield where the contaminants can react with gettering material.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: October 9, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Hougong Wang, Steve Lai, Gongda Yao, Peijun Ding
  • Patent number: 6287977
    Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: September 11, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Imran Hashim, Tony Chiang, Barry Chin
  • Patent number: 6193811
    Abstract: Methods for baking-out and for cooling a vacuum chamber are provided. In a first aspect, an inert gas which conducts heat from the vacuum chamber's bake-out lamps to the shield and from the shield to the other parts within the vacuum chamber is introduced to the chamber during chamber bake-out. The inert gas preferably comprises argon, helium or nitrogen and preferably raises the chamber pressure to about 500 Torr during chamber bake-out. A semiconductor processing apparatus also is provided having a controller programmed to perform the inventive bake-out method. In a second aspect, a process chamber is provided having at least one source of a cooling gas. The cooling gas is input to the chamber and is allowed to thermally communicate with the chamber body and components. The cooling gas may reside in the chamber for a period of time or may be continuously flowed through the chamber. Once the chamber reaches a target temperature the cooling gas is evacuated.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: February 27, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Arvind Sundarrajan, Dinesh Saigal, Peijun Ding, James van Gogh
  • Patent number: 6182376
    Abstract: An apparatus and method is provided for capturing, heating and degassing a wafer without using moving parts and without exposing the wafer to external stress. A degassing chamber is backfilled with a dry gas that improves wafer heating ramp rates and wafer heating uniformity. The backfilled gas efficiently conducts heat at relatively low pressures. Thus the degassing chamber may be evacuated via a cryo-pump without the need for an intermediate rough pumping step. Further, because the wafer is heated primarily by conduction, wafer temperatures are easily and precisely controlled independent of layers previously deposited on the wafer. Frontside heating elements such as heat generators and/or heat reflectors are provided that further improve wafer heating ramp rates and wafer heating uniformity by directing heat toward the front surface of the wafer. Preferably as heat radiates from the wafer it is reflected back to the wafer by a frontside reflector.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: February 6, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Ho Seon Shin, Dan Marohl
  • Patent number: 6139701
    Abstract: A copper sputtering target is provided for producing copper films having reduced in-film defect densities. In addition to reducing dielectric inclusion content of the copper target material, the hardness of the copper target is maintained within a range greater than 45 Rockwell. Within this range defect generation from arc-induced mechanical failure is reduced. Preferably hardness is achieved by limiting grain size to less than 50 microns, and most preferably to less than 25 microns. The surface roughness preferably is limited to less than 20 micro inches, or more preferably, less than 5 micro inches to reduce defect generation from field-enhanced emission. This grain size range preferably is achieved by limiting the purity level of the copper target material to a level less than 99.9999%, preferably within a range between 99.995% to 99.9999%, while reducing particular impurity levels.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: October 31, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Vikram Pavate, Seshadri Ramaswami, Murali Abburi, Murali Narasimhan
  • Patent number: 6139698
    Abstract: A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: October 31, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Hougong Wang, Gongda Yao
  • Patent number: 6113698
    Abstract: An apparatus and method for clamping and heating a wafer without using moving parts and without exposing the wafer to external stress is provided. A high backside wafer pressure which provides efficient heat transfer from a heated substrate support to the wafer is offset by a high frontside wafer pressure higher than or lower than the backside wafer pressure. The high frontside pressure reduces wafer stress by providing a uniform frontside/backside pressure and presses the wafer against the heated substrate support. A continuous gas purge for providing a viscous flow across the wafer to carry away desorbed contaminants, and frontside heating elements for improving desorption are provided.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: September 5, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Ivo Raaijmakers, Dan Marohl