Abstract: An approach is provided that receives a request to perform an action by an information handling system that includes a processor. In response to the request, a captcha request that corresponds to a captcha is transmitted to a foldable display screen. A response is received from the foldable display screen with the response including one or more bends of the foldable display screen. The received one or more bends are compared to one or more expected bends included in the captcha. The requested action is performed in response to the comparison revealing that the received one or more bends match the one or more expected bends. On the other hand, performance of the requested action is inhibited in response to the comparison revealing that at least one of the received one or more bends fails to match at least one of the one or more expected bends.

Abstract: An approach is provided that receives an alteration request to mark a selected column in a database table as an unused column. A database control table is then updated to indicate that the selected column is unused. After the database control table is updated, when a read request is received for the selected column, the same data is returned for the selected column for each row being read and this data is not stored in the database table.

Abstract: An approach is provided to establish, over a network adapter, network sessions with various client computer systems. Requests for a webpage are received at the network adapter from the client computer systems. The requested webpage is retrieved from a storage area. Multiple timeout intervals are initialized and stored in a memory area, wherein each of the plurality timeout intervals corresponds to one of the client computer systems. The timeout intervals that are initialized are different for at least some of the client computer systems. The requested webpage is returned to the client computer systems. When a timeout interval elapses for any of the client computer systems, the system terminates the session that was established with the client computer system.

Abstract: An approach is provided that allows an administrator to set a new password at a wireless access point, such as a traditional WAP or a wireless router. The wireless access point creates a message that includes the new password. The message is encrypted using the old password that was previously set for the wireless network. The encrypted message is wirelessly transmitted from the wireless access point to the active client devices (those clients currently accessing the wireless network). The clients decrypt the message using the old password that was previously provided to the clients. The clients retrieve the new password from the message. The clients construct a new message that is encrypted using the new password. The new message is wirelessly transmitted from the clients to the wireless access device and serves as an acknowledgement.

Abstract: An optimization engine includes a mixed-integer programming (MIP) solver that receives a programming model, an outcome objective, and a group of start vectors. Each of the MIP start vectors in the group specify one or more restrictions to apply to the programming model. The MIP solver uses the programming model to compute a potential solution from each of the MIP start vectors included in the group, which results in a group of potential solutions. Next, the MIP solver selects one of the potential solutions in the group as an optimal intra-group solution. The optimal intra-group solution is the potential solution in the group that best achieves the outcome objective. In turn, the optimal intra-group solution is used to complete the outcome objective.

Abstract: A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to branch to a piggyback interrupt handler corresponding to a piggyback interrupt vector. Based upon the determination, the hypervisor either branches to the piggyback interrupt handler or to an administrating interrupt handler that corresponds to the administrating interrupt vector.

Abstract: Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime alignment. Length conversion operations, for packing and unpacking data values, are included in the alignment handling framework. These operations are formally defined in terms of standard SIMD instructions that are readily available on various SIMD platforms. This allows sequential loop code operating on datatypes of disparate length to be transformed (“simdized”) into optimized SIMD code through a fully automated process.

Abstract: A system, method, and program product are provided that identifies a cache set using Translation LookAside Buffer (TLB) attributes. When a virtual address is requested, the method, system, and program product identifies a cache set using buffer attributes. When a virtual address is received, an attempt is made to load the received virtual address from a cache. When the attempt results in a cache miss, a page is identified within a Translation LookAside Buffer that includes the virtual address. A class identifier is then retrieved from the identified page, with the class identifier identifying a cache set that is selected from the cache.

Abstract: A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.

Abstract: An approach is provided that uses policies to determine which parental privileges are inherited by the parent's child processes. A parent software process initializes a child software process, such as by executing the child process. The parent process is associated with a first set of privileges. The inheritance policies are retrieved that correspond to the parent process. A second set of privileges is identified based on the retrieved inheritance policies, and this second set of privileges is applied to the child software process.

Abstract: A system, method and program product that securely saves and restores the context of a secure program loader is presented. An interrupt is sent to a secured program running on an special purpose processor core that is running in isolation mode. The special purpose processor core is included in a heterogeneous processing environment that includes the special purpose processor cores (including the isolated special purpose processor core), and one or more general purpose processors. Each of the processors can access a shared memory. The isolated special purpose processor core includes a local memory that is inaccessible from the other processors. The system encrypts the secured program's context using a randomly generated encryption key and stores the context in the shared memory. A secure loader's context is updated with the generated encryption key and then the secure loader's context is saved to the shared memory.

Abstract: An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirements of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residual iteration counts, and multiple statements with arbitrary alignment combinations. Loop peeling is used to reduce the computational overhead associated with misaligned data. A loop prologue and epilogue are peeled from individual iterations in the simdized loop, and vector-splicing instructions are applied to the peeled iterations, while the steady-state loop body incurs no additional computational overhead.

Abstract: Methods, apparatus, or products for displaying an image of an object placed on a surface computer, the surface computer including a surface, surface computer capable receiving multi-touch input through the surface and rendering display output on the surface, the surface computer including a scanner, that include: detecting, by the surface computer, an object placed on the surface; identifying, by the surface computer, a region of the surface upon which the object is placed; scanning, by the surface computer using the scanner, the identified region of the surface to create an object image of the object; and rendering, by the surface computer, the object image within the identified region without modifying portions of any other images rendered on the surface outside the identified region.

Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.

Abstract: An approach is provided that receives web page data at a network adapter included in an information handling system. A process identifies a first set style sheets that apply to the web page data and a second set of style sheets that apply to graphical elements that are within a predefined proximity area of a cursor that is displayed on the information handling system's display screen. The process displays graphical elements that are outside the predefined proximity area using the first set of style sheets and simultaneously displays a second set of elements that are within the predefined proximity area using the second set of style sheets.

Abstract: A system and method for dividing an application into a number of logical program partitions is presented. Each of these logical program partitions are stored in a logical program package along with a execution monitor. The execution monitor runs in one of the processing environments of a heterogeneous processing environment. The logical program partition includes sets of object code for executing on each of the types of processors included in the heterogeneous processing environment. The logical program partition includes instrumentation data used to evaluate the performance of a currently executing partition. The execution monitor compares the instrumentation data to the gathered profile data. If the execution monitor determines that the partition is performing poorly then the code for the other environment is retrieved from the logical program package and loaded and executed on the other environment.

Abstract: A system and method for incorporating social networking maps in collaboration tools is presented. A user creates rules that are based upon the user's relationship with other users and provides the rules to a network server. The network server uses these rules when the network server receives a relational request from the collaboration tool in order to filter a hierarchal social networking map. The hierarchal social networking map is centrally located such that different collaboration types may utilize the hierarchal social networking map. After filtering the hierarchal social networking map, the network server sends a list of user identifiers to the collaboration tool, which allows the user to collaborate with recipient users corresponding to the list of user identifiers, which are users that share a particular relationship with the user.

Abstract: Processor resources are partitioned based on memory usage. A compiler determines the extent to which a process is memory-bound and accordingly divides the process into a number of threads. When a first thread encounters a prolonged instruction, the compiler inserts a conditional branch to a second thread. When the second thread encounters a prolonged instruction, a conditional branch to a third thread is executed. This continues until the last thread conditionally branches back to the first thread. An indirect segmented register file is used so that the “return to” and “branch to” logical registers within each thread are the same (e.g., R1 and R2) for each thread. These logical registers are mapped to hardware registers that store actual addresses. The indirect mapping is altered to bypass completed threads. When the last thread completes it may signal an external process.

Abstract: A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.

Abstract: A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available (i.e., is not contended), the only data gathered is a counter that is incremented to keep track of the number of times the particular lock was requested. When a lock is contended, an operating system trace hook is requested. The trace hook records data such as the timestamp that the requester requested the lock, the request count, a stack traceback to identify the function corresponding to the requester, and the address of the lock that was requested. Post-operative processing analyzes the recorded trace hook data to identify contended locks and processes that may not be efficiently using locks.