Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A low voltage semi-folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dimensions.

Abstract: “Context” of an environment or area is considered to be one or more characteristics of the environment or area, manifested by the presence of various types of equipment or devices. Detection of various types of devices and equipment in a localized area is by way of short-range wireless signals over which data about the devices is transmitted to one or more subscriber units. The subscriber units can forward context-determinative data and information to a service provider which can vicariously use the equipment or devices in the area via the subscriber device.

Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.

Abstract: A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus.

Abstract: A wireless receiver and method employs a forward/backward recursive covariance based filter coefficient generation scheme for equalizing a received wireless signal, such as a CDMA signal or other suitable signal. A forward/backward recursive covariance based filter coefficient generating circuit (206) includes a forward recursion portion (300) that receives data representing channel estimates (18) of a communication channel, and data representing an auto-covariance matrix (22). The forward recursion portion (300) produces a set of output values (306) from each iteration stage (400a–400n) of the forward recursion portion (300). The set of output values (306) are stored and a backward recursion portion (302) obtains the set of output values (306) and also receives the data representing the auto-covariance matrix (22), and generates filter coefficients (208) based on this information.

Abstract: A system for traversing and rendering a graphic primitive, comprising a setup engine that outputs representative values of a graphic primitive; and a raster engine that receives the representative values of the graphic primitive and forms therefrom representative pixels, the raster engine having at least a scan module that scans only pixels within the graphic primitive and assigns data values to each of the pixels and a look-ahead module that identifies pixels that are inside of the primitive.

Abstract: An organizer case comprising a tray having a bottom wall and a plurality of compartment walls formed unitarily with and upstanding from said bottom wall, at least two of said walls extending in parallel relation and spaced apart a separation distance, said two of said walls having confronting sidewall faces each having a plurality of first joint formers spaced therealong, a first set of insert dividers each dimensioned to extend non-orthogonally between said sidewall faces, a second set of insert dividers each dimensioned to extend orthogonally between said sidewall faces, the dividers of each said set each having opposed side edge flange portions having second joint formers for friction fit engagement with said first joint formers, said side edge flange portions of each of the dividers of said first set being spaced apart a distance at least about 20% greater than said separation distance.

Abstract: A method and apparatus for parallel processing of pixel information within a video graphics circuit is accomplished when the video graphics circuit includes a set-up engine, an edgewalker circuit, a span processing circuit, and a plurality of pixel processing circuits. In such an embodiment, the set-up engine receives vertex information and produces object-element information therefrom. The object-element information is provided to the edgewalker circuit, which in turn produces span definition information. The span definition information identifies the starting pixel of a span and the starting pixel parameters. The span information is received by the processing circuit and converted into a plurality of pixel parameters. The plurality of pixel parameters are provided to the plurality of pixel processing circuits wherein each of the plurality of pixel processing circuits processes corresponding pixel parameters to produce pixel information in accordance with the information provided by the processing circuit.

Abstract: A transmitter circuit (200, 400, 510) and method reduces amplitude modulation distortion in an amplifier (210). The transmitter circuit (200, 400, 510) includes a power control error data generator (230), a feedforward predistortion data generator (240), feedforward adder logic (250) and the amplifier (210). The power control error data generator (230) receives amplitude modulation data (252) and an RF coupled output signal (254) and, in response, produces power control error data (256). The feedforward predistortion data generator (240) receives the amplitude modulation data (252) and, in response, produces feedforward predistortion data (258). The feedforward adder logic (250) receives the power control error data (256) and the feedforward predistortion data (258) and, in response, produces power control data (260).

Abstract: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across at least one of the electrical leads associated with the carrier substrate. Thereupon, system instructions may be stored and retrieved from the system memory through the information router within the integrated circuit on the standard dimension carrier substrate.

Abstract: A method and apparatus utilizes a three dimensional rendering engine to rotate an image based on user selected or otherwise determined screen orientation. A vertex coordinate transformation is defined for a rotated destination image. The source image is used as a texture for texture mapping during rendering operation to produce rotated image. In one embodiment, a separate set of software instructions is used for each orientation mode. Accordingly, a non-pixel by pixel based 3D rotation may be carried out using a 3D rendering engine to avoid a single parameter based seriatim pixel by pixel based orientation.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of accumulation registers is provided for storing the results of an adder, wherein each of the plurality of accumulation registers corresponds to a different thread of the plurality of threads. The contents of each of the plurality of accumulation registers can be selected as an input to the adder such that the present accumulated value can be added to a subsequently calculated produce to generate a new accumulated value.

Abstract: A graphics processing circuit includes a line end generation circuit operative to generate line aligned end cap data in response to primitive data; and a rasterizer, coupled to the line end generation circuit, operative to generate pixel data representing a line to be rendered, the pixel data including the line aligned end cap data. A graphics processing method includes receiving primitive data for a line to be rendered, the primitive data including start endpoint data and stop endpoint data, determining the height and width of the line in screen space, determining line end cap orientation with respect to the line to be rendered, and determining vertices that define the line to be rendered, wherein the vertices define end caps aligned with the line to be rendered.

Abstract: A case for storage and transportation of sporting equipment including a case section defining an interior cavity. At least one clamp disposed within the interior cavity including a body portion and a jaw portion. The jaw portion is movable relative to the body portion to fasten and unfasten sporting equipment with respect to the case.

Abstract: An assist drive assembly for adjusting tension in a web generated when the web is moved over a roller in a contacting relationship therewith. A plurality of north and south pole elements are disposed about the roller. A controller is coupled to a magnetic pole sensor and an magnetic coil. The magnetic pole sensor and magnetic coil are disposed adjacent the north and south pole elements such that, when, during rotation of the roller in a direction of rotation, as a result of the web moving over the roller, the magnetic pole sensor observes a south pole element a first signal is generated that actuates the controller to energize the magnetic coil to generate a north pole field that attracts an immediately adjacent south pole element thereby imparting a torque to the roller in a direction of rotation of the roller.

Abstract: A display pointing device (10) includes a fingerprint sensing circuit (18) that optically senses, for example, a portion of a fingerprint or other skin texture, and a fingerprint movement detection circuit (20), operatively coupled to the fingerprint sensing circuit (18), that is operative to determine a direction of movement and a rate of movement of skin texture being sensed by the fingerprint sensing circuit (18) to produce pointing output data (24) for a display (12). The pointing output data (24) may be, for example, data representing a visual indication of a position on a display screen, such as a position of a cursor or of highlighted text, or any other suitable position indication. A method for providing pointing information for display includes sensing a fingerprint, determining a direction of movement and a rate of movement of the fingerprint and producing a pointing output for display based on a determined direction of movement and rate of movement of the sensed fingerprint.

Abstract: A video processor integrates the processing of video and graphics data by restructuring the discrete blocks of luminance and chrominance component data associated with video image data (Y,U,V) into composite pixel values (YUYV), and performing the subsequent processing, in particular motion compensation, upon this composite data form. The discrete blocks of video image data are queue and processed in parallel to form a composite pixel value associated with each pixel within the image areas represented by the discrete blocks. By forming composite pixel values for reference data and error term data, common processing elements can be optimized and used for both video and graphics image processing. For example, the trilinear interpolator commonly used for 3-D graphics filtering and texturing can be used to form predicted macroblocks for motion compensation, and the specular adder used for graphics lighting effects can be used to process the motion compensation error terms.

Abstract: A circuit and method for providing a tunable capacitance for a voltage control oscillator (VCO) in which at least one P-N junction varactor and at least one metal oxide semiconductor (MOS) accumulation-mode varactor are effectively coupled and tuned in parallel, thereby providing a net tunable capacitance with which the VCO will realize an optimal combination of quality factor, phase noise, and gain characteristics.