Abstract: A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration. One implementation of the apparatus includes one or more DMA channel interfaces providing a series of DMA channel requests such that a DMA channel request for a next DMA transfer is provided before a current DMA transfer is completed; and a DMA controller that initiates arbitration of DMA channel requests after they are provided by the one or more DMA channel interfaces and before the current DMA transfer is completed, and initiates set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration.

Abstract: A method for automatically recording snapshots of a computer screen during a computer session for later playback, comprises receiving a start indication, and automatically recording snapshots of a computer screen periodically during the computer session after the start indication is reached. An apparatus for performing such function comprises a frame buffer for storing snapshots of the computer screen, a FIFO cache memory, a mass storage memory, and programmed means. The programmed means receives a start indication, periodically copies data from the frame buffer to the FIFO cache memory during a computer session after the start indication is reached, and compresses the stored data before storing it the mass storage memory for later playback.

Abstract: An apparatus and method for generating a compensated percent-of-clock period delay signal are described. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal.

Abstract: A method is described that is implemented by a server for securely providing a text file to a client for execution. The method includes providing an encrypted text file and a program facilitating execution of the encrypted text file to the client. Such providing may be over the Internet or using a computer readable medium such as compact disc. The provided program responds to a run command to decrypt the encrypted text file, and feed the decrypted text file to an interpreter for execution.

Abstract: Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species is generated by creating free radicals, and combining the free radicals to form the chemical species at the point of use.

Abstract: A content addressable memory with programmable priority weighting and low cost match detection is described. A CAM array provides match and no-match indications of an input data word to a weight array. The weight array generates a forced match with an assigned weight that is lower than those assigned to match and no-match indications received from the CAM array. The weight array determines a winning match among the received match indications and the forced match according to their assigned weights, and provides an indication of the winning match to an encoder. The encoder provides an address of the winning match, and a match detect output which is generated from the success or lack thereof of the forced match being determined the winning match.

Abstract: A method and apparatus for rendering an integrated circuit design layout is described. Graphics files are generated for selected zoom-in factors from cell-based information of the integrated circuit design, and stored in memory. When a computer operator selects a zoom-in factor greater by a predetermined amount than the largest of such selected zoom-in factors, a selector enables a rendering engine to render the integrated circuit design layout from the cell-based information. On the other hand, when the computer operator selects a zoom-in factor less than the largest of such selected zoom-in factors plus the predetermined amount, the selector enables a graphics processor to render the integrated circuit design layout from appropriate ones of the graphics files.

Abstract: A method generates information for a window view of an integrated circuit from layout-formatted data such as GDSII formatted data. The method includes generating outer boundary boxes for structures of the integrated circuit from the layout-formatted data, generating a build file by including information of structures having outer boundary boxes completely or partially in a window, and generating information of the window view from the information thus included in the build file. In generating the build file, information of structures having outer boundary boxes completely outside the window are excluded from the build file. Also excluded is information of structures having areas less than a threshold value.

Abstract: A method and apparatus for inserting antenna diodes into an integrated circuit design is described. During the design process, diode cells are placed in filler cells of the integrated circuit design, but left unconnected. Subsequently, when an ECO is received requiring antenna diodes to be inserted in the integrated circuit design, only metal mask changes are required to connect the diode cells to gate electrodes of specified transistors or cells. Since the diode cells are already part of the original integrated circuit design layout, it is not necessary to perform a re-layout of the design cells with the diode cells performing antenna diode functions, thereby speeding up the EDA redesign process as well.

Abstract: A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer.

Abstract: A communication interface unit (128) facilitates data word exchanges between a parallel driven bus (210) and a serial driven communication channel (136) by performing both parallel-to-serial and serial-to-parallel data conversion functions. A transmitter circuit (200) is included in the communication interface unit (128), which performs parallel-to-serial data conversion employing a multiplexer circuit (204) and control logic circuitry (208). The multiplexer circuit (204) concurrently receives a plurality of data bits of a data word being transferred, and the control logic circuitry (208) thereupon causes the plurality of data bits of the data word to be successively passed through the multiplexer circuit (204) so as to perform parallel-to-serial conversion. A receiver circuit (300) may also be included in the communication interface unit (128), which performs serial-to-parallel data conversion employing a plurality of flip-flops (304) and control logic circuitry (308).

Abstract: A mechanism to allow dynamic configurations and/or diagnostic of a computer system from a remote location is provided. The computer system receives instruction codes of a program from a data source. When executed by the CPU, the instruction codes performs the necessary erase and program operations to embed a firmware program onto to the flash memory. The firmware program can be used for configurations or diagnostic purpose.

Abstract: A computer system includes a host processor, a system memory, a display unit, a pointer device, a VGA controller, and a display memory. The VGA controller communicates with the display memory through an 8-byte wide data bus such that each byte is controlled by a separate column address strobe.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.

Abstract: A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, a biasing circuit for providing a bias voltage to each of the voltage controlled inverting delay cells, and a source-follower transistor for providing a control voltage to the biasing circuit and voltage controlled inverting delay cells. Each of the voltage controlled inverting delay cells includes a first and a second plurality of transistors which define two outputs of the voltage controlled inverting delay cell, and a clipper transistor connected between the two outputs to short them together whenever a difference between a bias voltage provided to a gate of the clipper transistor by the biasing circuit and a voltage on either one of the two outputs exceeds a threshold voltage of the clipper transistor.