Abstract: A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.

Abstract: Modulo timer apparatus including a chain of modulo counter stages is controllable by write signals generated by a central controller. The central controller is operative to generate a write signal corresponding to a selected counter stage, and a digital control signal. The initial counter stage of the chain includes a selecting circuit controlled by the digital control signal to couple either a reference clock signal or the corresponding write signal to the initial counter stage to alter the count thereof. Each successive counter stage includes a corresponding selecting circuit also controlled by the digital control signal to couple either a pulse signal generated from the preceding counter stage as it counts through its modulus value or the corresponding write signal to the successive counter stage to alter the count thereof.

Abstract: Two or more crystal filter blanks are mounted together in such a manner so as to minimize the printed circuit board surface area occupied by their aggregate footprint and to minimize the vibratory and oscillatory interference among the cyrstal filters. Mounting devices are coupled to a first nonvibratory node and a second nonvibratory node of the crystal blanks to minimize vibrational and oscillatory interference between the crystal filters. Insulating material is disposed between the crystal blanks for electrically insulating and physically separating the crystal blanks from each other to additionally minimize electrical and vibrational interference between the crystal blanks.

Abstract: A receiver (200) includes an automatic frequency controller that determines the frequency of a receiver signal, and a calculates a frequency error from the received signal. The frequency error is used to calculate a correction factor (316) that is used to adjust the frequency of an oscillator (308) in response to the determined error.

Abstract: A selective call controller, such as a paging terminal, and a method therefor is provided for receiving calls comprising first and second types of signal, such as numeric/alphanumeric or modem/DTMF. A determination is made of the type of signal being received, and a destination address and message signal is selected accordingly.

Abstract: An apparatus for effecting a vibrating motion comprises a resonant planar armature, a housing, an electromagnetic device attached to the housing for effecting an alternating electromagnetic field, a magnetic device coupled to the armature and to the electromagnetic field for alternatively moving the armature in a first and a second direction in response to the electromagnetic field. The resonant planar armature comprises a plurality of planar spring members arranged regularly about a central planar region within a planar perimeter region of the armature, and the spring members provide a restoring force normal to a movement of the central region of the armature caused by the alternating electromagnetic field.

Abstract: A selective call receiver displays messages in at least two scripts. The selective call receiver receives data including an address and a message to be displayed. A decoder decodes the data and recognizes a script select character therewithin. A memory stores at least two fonts corresponding to said at least two scripts, said scripts having different resolutions. A microcomputer is coupled to the decoder and the memory for selecting one of the fonts in response to the script select character, and a display is coupled to the microcomputer for displaying the message in the selected font.

Abstract: A digital synchronizer examines a signal transmitted at a predetermined baud rate for a predetermined time. Upon completion of the predetermined time, a decision is made as to whether or not the signal included the predetermined baud rate. If the signal includes the predetermined baud rate, a bit clock is established indicative of the boundaries and center of each baud symbol. The synchronizer samples the signal at a multiple of the baud rate and accumulates the phase relationship between the samples and transitions of the signal during the predetermined time. Upon conclusion of the predetermined time, the distribution of the phase relationships is examined and the presence or absence of signal is determined. If the presence is determined, the bit clock is established.

Abstract: A three dimensional cellular communication system comprising a plurality of cells arranged in a multi-level environment to reduce interference and improve frequency reuse in both horizontal and vertical directions by offsetting cells stacked on different levels of the multi-level environment.

Abstract: An electrical circuit (200) comprises a first circuit (208) constructed and arranged to simulate an inductor and a second circuit (210) constructed and arranged to simulate an inductor. Coupled to these circuits is a third circuit (212) for simulating a mutual inductance therebetween.

Abstract: A sealing apparatus supplies one or more activating gases needed to produce a current generating chemical reaction in an air breathing battery, the supply of one or more activating gases being proportionally controlled to coincide with differing current loads.

Abstract: A circuit (200) for generating a first (EL1) and second (EL2) drive signals and limiting a maximum voltage of each of the drive signals (EL1, EL2). The circuit (200) further samples the drive signals (EL1, EL2) to provide a voltage source (Vdd).

Abstract: A paging receiver receives a message signal having an address field and a data field. The message has at least one address within the address field and a plurality of packets in the data field. The data packets contain a predetermined amount of information. A method for conserving power during reception of a message signal having an address field comprising a number of addresses involves entering the power conserving mode of operation after attempting to correlate a predetermined number of addresses with the paging receiver's address, where the predetermined number is less than the number of addresses in the address field. In addition, message information may be included within a plurality of packets by several methods including placing a corresponding plurality of addresses in the address field, each address indicating the occurrence of message information, or by indicating in one packet that information follows in a subsequent packet.

Abstract: A portable receiver has a time of day clock and receives a signal indicative of the location of the portable receiver. The portable receiver has a memory which has a plurality of locations with corresponding time zones. Upon reception of the location signal, the receiver determines the time zone of the location and the time zone of the time of day clock. The time of day clock is then adjusted to correspond to the time zone of the location. The location signal may also be used to adjust the operating frequency of the receiver.

Abstract: A selective call receiver includes a fiber optic channel located along the length of at least one side thereof for providing a visual alert of a received message.

Abstract: An electronic system having a plurality of resettable modules, such as memories and input/output circuits, wherein the modules are selectively, individually resettable by providing each module with a specific time slot during which it can receive a reset signal and be reset. The reset signal either is not supplied to other modules outside of their individual time slots, in the case of a multiplexed bus, or has no effect until a time slot signal is applied in coincidence therewith.

Abstract: A computing system has a predetermined minimum operating voltage. A method of operation thereof comprises the step of determining the predetermined minimum operating voltage of the system by operating the computing system at a plurality of different operating voltages until the computing system operates unsatisfactorily; and selecting the operating voltage of the system at a level greater than the unsatisfactory operating voltage.