Abstract: An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.

Abstract: In a successive-approximation charge-redistribution analog-to-digital converter which includes a binary weighted capacitive ladder network, an unknown analog input voltage is sampled only on the largest capacitor representing half the capacitance. The conversion phase proceeds utilizing all the capacitance and only half the reference voltage. This not only reduces circuit complexity, but also reduces problems associated with disruption of the charge stored on the capacitor.

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic is capable of handling serial communications in either the NRZ or Manchester (biphase) format. The result is more versatile and more reliable serial communications.

Abstract: A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register.

Abstract: An MOS logic circuit is provided which generates and latches an output signal at a given logic level upon detection of a given transition in an input signal coinciding with a given state of a clock signal. The circuit utilizes the capacitance inherent in an MOS structure. The circuit requires a minimum of MOS components and is therefore useful in high density MOS integrated circuits where it is desired to detect and latch a transition in a signal.The edge sense latch comprises an MOS inverter (Q1, Q2) responsive to an input signal S, a transmission gate (Q3) controlled by a clock signal, a transmission gate (Q4) controlled in part by an inherent capacitance (29), a latch comprising a pair of cross-coupled MOS transistors (Q5, Q8) for generating an output signal Q, and an MOS transistor (Q6) responsive to a reset signal R.

Abstract: There is provided a microprocessor interface circuitry which allows single peripheral and memory devices to be used with at least two different types of microprocessors. The interface includes a latch which latches the state of a control signal provided to the peripheral/memory device by the microprocessor. The control signal that is latched serves a somewhat different function when eminating from each of the at least two different microprocessors, and as such has different logic states. Logic circuitry is controlled by the latch to take at least one other control signal and generate the internal control signals used by the peripheral/memory device.

Abstract: This invention relates to a method and apparatus for producing the 135 Hz modulation component which is superimposed as the ninth harmonic on a 15 Hz component thereby producing the normally required Tacan radiation pattern. A cylindrical antenna is employed having located on and around its surface active elements such as dipoles. The 135 Hz component is produced by step-wise rotation of a binary current distribution around the cylindrical array of active elements. Since the system is binary, only two current states are employed, each having a predeterminedamplitude and phase. A predetermined number of the active elements are excited by one of the signals, and the remainder of the elements are excited by the second signal. This excitation is electronically rotated in a non-symmetric manner around the cylindrical array, thereby producing the required 135 Hz component.

Abstract: An adapter is provided for insertion between a conventional DME airborne interrogator and antenna. The adpater converts conventional interrogations into phase-coded or amplitude coded signals which are received by new Microwave Landing System (MLS) transponders. Each transponder will process interrogations having the correct code and frequency and will respond with precision reply signals. The precision replies are then received by the airborne equipment, converted back to standard reply pulses and processed to provide distance measurement. Also provided is a new transponder for use at MLS sites.

Abstract: The invention provides a superheterodyne receiver having a digitally adjustable tuning arrangement which permits wide adjustable frequency ranges and in which nearly no deviation from the adjusted frequency occurs over the entire adjustable frequency range.

Abstract: A surface acoustic wave delay line uses a closed loop principle with separate input and output transducers side by side. 3dB Multistrip couplers are introduced to achieve substantially 100% transfer for surface acoustic wave energy from the propagation path associated with the input transducer to the propagation path associated with the output transducer. Several such delay lines can be formed on a single cylindrical body of piezoelectric material and these can then be cascaded with intermediate amplification to form a long delay or a tapped delay.

Abstract: A special purpose microprocessor with a limited number of functions, which can be used to interface between a central processor and a portion of a telephone exchange--for example, in line scanning. Six bit addressing and decoding are employed with two logic elements performing the few available programs. The processor includes a random access memory for intermediate storage, one logic unit and has capacity for 64 memory locations. The logic unit includes two NAND gates.

Abstract: This relates to a channeling scheme for introducing a new service in the TACAN frequency band which can operate independently of the conventional TACAN system or in conjunction with it. Specifically, the new service is that of providing precision DME for a microwave landing system and for allowing existing TACAN airborne sets, when equipped with an adapter, to utilize new MLS ground beacons. In one channeling scheme, interrogations occur in frequency bands adjacent the standard TACAN interrogation band, and ground transmissions occur in frequency bands presently occupied by X mode reply signals. In a second scheme, which contemplates the use of standard airborne equipment provided with an adapter, interrogations occur within the conventional TACAN interrogation band, and replies occur in the bands now occupied by X mode reply signals.

Abstract: This relates to a temperature-compensated zener diode arrangement in the form of a semiconductor integrated circuit which consists of several transistor structures disposed in a common semiconductor body and interconnected by deposited metallizations. The base-emitter pn junctions of the transistor structures are so connected in series with respect to the direction of the total current flowing during operation that some of them are operated in the reverse direction up to the breakdown region as zener diodes and the remainder in the forward direction as forward bias diodes. The emitter of the first transistor structure acting as a zener diode or the base of a transistor structure acting as a forward bias diode, as well as the collector of the latter transistor structure, are connected to the first external terminal. The emitter of the latter transistor structure, acting as a forward bias diode, is connected to the second external terminal.

Abstract: For the handling, especially sorting, of devices which at least partly consist of a ferromagnetic material, at least one switchable electromagnet in a fixed position produces an electromagnetic field which penetrates a first steady magnetic field and is dimensioned and timely switched according to the special handling process to be performed.

Abstract: This invention relates to a bucket brigade circuit or delay line wherein there is provided frequency-dependent compensation of the signal attenuation after n-stages of the circuit. The compensation circuit contains a differential amplifier and a transferring circuit adding the frequency dependent signal loss to the bucket brigade line signal. The differential amplifier samples the signal of two adjacent stages controlled by the same clock signal phase.

Abstract: This invention relates to a bucket brigade circuit or delay line having a compensation circuit for the loss of the dc level after n stages. The compensation circuit contains a differential amplifer and a transferring circuit adding the dc level loss to the bucket brigade line dc level. The differential amplifier samples the signals of a line stage close to the input and a line stage far from the input which are both controlled by the same signal phase.

Abstract: An apparatus is provided for detecting digital pulses or pulse intervals and any combination thereof. Logic means is provided wherein the complement of the interval to be measured is loaded into a digital counter, and certain states of this counter are decoded to set and reset, respectively, an in-bin flip-flop. Operation is initiated when a digital input is received. If the interval to be measured terminates while the in-bin flip-flop is set, an output is generated indicating that a "hit" has been scored and the parameters of the measurement can be read out. Code words stored in a memory provide the specific parameters of measurement, and particular portions of the code words are employed depending on the desired mode of operation.

Abstract: PIN diodes are ineffective as waveguide switches because the device and its connecting leads behave in total as an inductive obstacle.There is described herein a method of converting the resultant obstacle into a broad band series resonant circuit which may be switched into two states. With the diode conducting, the obstacle appears as a short-circuit across the guide. With the diode nonconducting, the obstacle appears as an open circuit across the guide.

Abstract: This relates to a monolithically integrable circuit for providing an effective constant voltage to automobile instruments; fuel, temperature, etc. The standard bi-metallic switch is replaced by a power amplifier which is turned on and off by a Schmidt trigger circuit. A capacitor charge/discharge circuit is charged by a current source, the output of which varies with output voltage. When the switch level of the Schmidt trigger is reached, the power amplifier is turned off and the output grounded via the instruments. This turns off the charging source and turns on a discharging source. In this manner, the on/off ratio of the output is varied to supply an effective constant voltage to the instruments.

Abstract: This invention relates to an optical waveguide switch and directional coupler providing variable coupling between two optical fibers. The coupler is fabricated in semiconductive material such as GaAs or GaAlAs. A double heterostructure is used having a higher index of refraction middle layer. Optical fibers are inserted in channels in the semiconductive material. Varying the reverse bias across the heterostructure junctions located in the material between the channels electrically changes the refractive index of the material and alters the coupling between the fibers. The device is applicable to switching in optical communication systems.